System and method for reducing power dissipation in an analog to digital converter

• US 7,821,436 B2
• Filed: 06/09/2007
• Issued: 10/26/2010
• Est. Priority Date: 06/08/2006
• Status: Expired due to Fees

• Current Assignee: Cosmic Circuits Pvt., Ltd. (Cadence Group)
• Original Assignee: Cosmic Circuits Pvt., Ltd. (Cadence Group)
• Inventors: Easwaran, Prakash, Bhowmik, Prasenjit, Srinivasan, Chakravarthy, Krishnan, Sundararajan, Kali Bhattacharya, Prasun, Kumar Ghosh, Sanjeeb, Khatri, Mukesh, Chakkirala, Sumanth, Lakshminarayanan, Chandrashekar, Teeka Srinvasa Setty, Venkatesh
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US11/760,743
• Publication Number:
  US 20090295609A1
• Time in Patent Office: 1,235 Days
• Field of Search: 341/121, 341/120, 341/155, 341/156, 341/161, 341/162, 341/159, 341/165, 330/9, 327/124
• US Class Current: 341/121
• CPC Class Codes: H03M 1/0641 the dither being a random signal
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Claims

1. A method for reducing power dissipated in an analog to digital converter (ADC) comprised of a plurality of clock phases, each clock phase comprising an amplifying phase and a sample-and-hold phase for respectively amplifying and sampling an analog input signal, comprising the steps of:

(a) receiving, in a current amplifying phase, a residue value output from a residue amplifier in a previous clock phase; and

(b) amplifying said residue value during said current amplifying phase, thereby eliminating a load effect on said residue amplifier;

(c) driving a large load on the residue amplifier and increasing a feedback factor in the sample-and-hold phase and eliminating the sampling capacitance of a previous stage during a sample-and-hold phase, thereby eliminating a low feedback factor; and

(d) outputting the residue value from the residue amplifier at the termination of a sample-and-hold phase, the residue value being derived from said sampled analog input signal.

2. The method of claim 1, wherein power dissipated in said analog to digital converter (ADC) is reduced by sharing the large load on the residue amplifier between both said sample-and-hold phase and said amplifying phase.

3. A method for reducing power dissipated in an analog to digital converter (ADC), the method comprising the step of:

holding a residue value of a phase for two consecutive phases for each of a plurality of clock phases, whereby value input to a comparator is available for two consecutive phases, wherein said holding step further comprises;

calculating said residue value in said amplifying phase using a first set of comparators, said amplifying phase for amplifying an output of a previous sample-and-hold phase; and

selecting a threshold value of a second set of comparators in a subsequent sample-and-hold phase based on the residue value calculated at said calculating step.

4. The method of claim 3, wherein the number of comparators used in said analog to digital converter is reduced by sharing the residue value between two consecutive phases from among the plurality of clock phases whereby power dissipated is reduced.

5. The method of claim 3, wherein the holding step further comprises:

reducing the speed requirement on the comparator whereby reducing power dissipated.

6. The method of claim 3, wherein the sample-and-hold phase and the amplifying phase in each of said plurality of clock phases occur in a sequentially continuous manner.