Fully integrated tuner architecture

• US 7,821,581 B2
• Filed: 07/30/2008
• Issued: 10/26/2010
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Duncan, Ralph, Bult, Klaas, Carr, Frank, Kwan, Tom W., Khorramabadi, Haideh, Ward, Christopher M., Chang, James Y. C.
• Primary Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US12/219,925
• Publication Number:
  US 20080284919A1
• Time in Patent Office: 818 Days
• Field of Search: 348/731, 348725-727, 455/266, 455/296, 455313-315, 455/337, 455/302, 455338-340, 455/179.1, 455/207, 455/196.1, 455/305, 455/202, 455/205, 455/188.1, 455/208, 455/189.1, 455/209, 455/190.1, 455/303, 455/191.1, 725/151
• US Class Current: 348/726
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. An integrated receiver, comprising:

a substrate configured to provide a physical medium upon which a receiver circuit is disposed;

a first mixer, disposed upon the substrate, configured to upconvert a frequency of a received signal to a first intermediate frequency (IF);

a first filter bank, disposed upon the substrate, configured to filter an output of the first mixer, the first filter bank including a plurality of cascaded filters, each of the plurality of cascaded filters having a substantially identical frequency response; and

a second mixer, disposed upon the substrate, configured to downconvert a frequency of an output of the first filter bank from the first IF to a second IF.

2. The receiver of claim 1, wherein a frequency of the received signal is substantially less than a frequency of the first IF.

3. The receiver of claim 1, wherein a frequency of the first IF is substantially greater than a frequency of the second IF.

4. The receiver of claim 1, wherein the second mixer is an I/Q mixer that is configured to convert the frequency of the output of the first filter bank from the first IF to the second IF.

5. The receiver of claim 1, wherein the first mixer is configured to convert the received signal to the first IF using a first local oscillator (LO) signal.

6. The receiver of claim 5, further comprising:

a first LO generator, disposed on the integrated receiver substrate, configured to provide the first LO signal to the first mixer.

7. The receiver of claim 1, wherein the second mixer is configured to convert the first IF to the second IF using a second local LO signal.

8. The receiver of claim 7, further comprising:

a second LO generator, disposed on the integrated receiver substrate, configured to provide the second LO signal to the second mixer.

9. The receiver of claim 1, further comprising:

a third mixer, disposed upon the substrate, configured to convert a frequency of an output of the second mixer from the second IF to a third IF.

10. The receiver of claim 9, wherein the third mixer is an I/Q mixer that is configured to convert the frequency of the output of the second mixer from the second IF to the third IF.

11. The receiver of claim 9, wherein the third mixer is configured to convert the second IF to the third IF using a third local LO signal.

12. The receiver of claim 11, wherein the third LO signal is generated by dividing the second LO signal.

13. The receiver of claim 9, further comprising:

a second filter bank, disposed upon the substrate, configured to filter an output of the second mixer, wherein the third mixer is configured to convert a frequency of an output of the second filter bank from the second IF to the third IF.

14. The receiver of claim 13, wherein at least one of the first filter bank and the second filter bank is a plurality of LC band pass filters.

15. The receiver of claim 13, wherein the second filter bank has a center frequency substantially equal to the second IF.

16. The receiver of claim 1, wherein the first filter bank has a center frequency substantially equal to the first IF.

17. A method for processing a received signal, comprising:

(a) upconverting a frequency of the received signal to a first intermediate frequency (IF);

(b) filtering, by a first filter from among a plurality of cascaded filters, the converted signal from step (a);

(c) filtering, by a second filter from among the plurality of cascaded filters, the filtered signal from step (b), the first filter and the second filter having a substantially identical frequency response; and

(d) downconverting a frequency of the filtered signal from step (c) from the first IF to a second IF, wherein steps (a)-(d) are performed on a common substrate.

18. The method of claim 17, wherein step (a) comprises:

(a)(i) converting the received signal to the first IF using a first local oscillator (LO) signal.

19. The method of claim 18, wherein step (a) further comprises:

(a)(ii) generating the first LO signal using a first LO generator.

20. The method of claim 17, wherein step (d) comprises:

(d)(i) converting the first IF to the second IF using a second local LO signal.

21. The method of claim 20, wherein step (d) further comprises:

(d)(ii) generating the second LO signal using a second LO generator.

22. The method of claim 17, further comprising:

(e) converting a frequency of the converted signal from step (d) from the second IF to a third IF, wherein step (e) is performed on the common substrate.

23. The method of claim 22, wherein step (e) comprises:

)

(e)(i) converting the second IF to the third IF using a third local LO signal.

24. The method of claim 23, wherein step (e) further comprises:

(e)(ii) generating the third LO signal by dividing the second LO signal.

25. The method of claim 17, further comprising:

(e) filtering the converted signal from step (d), wherein step (e) is performed on the common substrate.

26. The method of claim 25, further comprising:

(f) converting a frequency of the filtered signal from step (e) from the second IF to a third IF, wherein step (f) is performed on the common substrate.

27. The method of claim 26, wherein step (f) comprises:

(f)(i) converting the second IF to the third IF using a third local LO signal.

28. The method of claim 27, wherein step (f) further comprises:

(f)(ii) generating the third LO signal is generated by dividing the second LO signal.