Flash multi-level threshold distribution scheme
First Claim
1. A Flash memory device comprising:
- a memory array having memory cells arranged in rows and columns, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable in a program operation to have at least one program threshold voltage in the erase voltage domain;
a wordline driver for selectively driving a wordline connected to a gate terminal of a memory cell with a programming voltage for changing the erase threshold voltage to the at least one program threshold voltage in the erase voltage domain during the program operation.
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Abstract
A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
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Citations
19 Claims
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1. A Flash memory device comprising:
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a memory array having memory cells arranged in rows and columns, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable in a program operation to have at least one program threshold voltage in the erase voltage domain; a wordline driver for selectively driving a wordline connected to a gate terminal of a memory cell with a programming voltage for changing the erase threshold voltage to the at least one program threshold voltage in the erase voltage domain during the program operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for storing data in a flash memory cell comprising:
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erasing the flash memory cell to have an erased state in an erase voltage domain; and
,programming the flash memory cell to have any one of a first portion of programmed states distinct from the erased state in the erase voltage domain and a second portion programmed states in a program voltage domain. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification