Flash memory device with redundant columns

• US 7,821,830 B2
• Filed: 07/23/2008
• Issued: 10/26/2010
• Est. Priority Date: 07/23/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yip, Aaron, Han, Jin-Man
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US12/178,192
• Publication Number:
  US 20100020609A1
• Time in Patent Office: 825 Days
• Field of Search: 365/185.09, 365/185.11, 365/189.02, 365/189.05, 365/200, 365/230.03, 365/230.04
• US Class Current: 365/185.09
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Claims

1. An apparatus comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of redundancy interleave groups of redundant columns;

a plurality of interleave groups of data latches, each of the interleave groups of data latches being configured to store data read from a respective one interleave group of regular columns;

a plurality of redundancy interleave groups of redundant data latches, each of the redundancy interleave groups of redundant data latches being configured to store data read from a respective one redundancy interleave group of redundant columns; and

a multiplexer configured to selectively output data from the plurality of interleave groups of data latches and the plurality of redundancy interleave groups of redundant data latches,

wherein the apparatus is configured to assign a redundant column in one of the redundancy interleave groups of redundant columns to replace a defective regular column in any one of the interleave groups of regular columns;

wherein the apparatus is further configured to allow switching among two or more interleaved read schemes.

2. The apparatus of claim 1, wherein the plurality of interleave groups of regular columns comprise a first group of regular columns and a second group of regular columns, and wherein the plurality of redundancy interleave groups of redundant columns comprise a third group of redundant columns and a fourth group of redundant columns.

3. The apparatus of claim 2, wherein the device is configured to map the column address of at least one regular column in the first group to a redundant column in the third group.

4. The apparatus of claim 3, wherein the device is further configured to map the column address of at least one regular column in the first group to a redundant column in the fourth group.

5. The apparatus of claim 4, wherein the plurality of interleave groups of regular columns comprise a fifth group of regular columns and a sixth group of regular columns, and wherein the plurality of redundancy interleave groups of redundant columns comprise a seventh group of redundant columns and an eighth group of redundant columns.

6. The apparatus of claim 5, wherein the device is configured to map the column address of at least one regular column in the first group to a redundant column in the seventh group.

7. The apparatus of claim 5, wherein the device is configured to map the column address of at least one regular column in the first group to a redundant column in the eighth group.

8. The apparatus of claim 1, further comprising a redundancy selector configured to select a redundant column at least partly in response to the column address of a regular column.

9. The apparatus of claim 8, wherein the redundancy selector comprises:

a plurality of column redundancy elements, each of the column redundancy elements being configured to receive the column address of a regular column and a programmed address, the programmed address indicating a defective regular column, and to output a redundancy signal indicative of whether the column address and the programmed address match each other; and

a first logic gate configured to perform an OR operation on the redundancy signals from the plurality of column redundancy elements, and to outputs a redundancy hit signal.

10. The apparatus of claim 9, wherein the device is configured to provide the multiplexer with a control signal allowing the multiplexer to selectively output data from the plurality of interleave groups of data latches, and wherein the device is further configured to disable the control signal at least partly in response to the redundancy hit signal.

11. The apparatus of claim 1, wherein the apparatus is configured to of switch among two or more of one-way, two-way, and four-way interleaved read schemes.

12. The apparatus of claim 1, wherein the apparatus is configured to perform an interleaved read scheme having the same number of ways as the number of the interleave groups when the number of defective columns in each of the interleave groups is equal to or less than the number of redundant columns in a respective one of the redundancy interleave groups.

13. The apparatus of claim 1, wherein the apparatus is configured to perform an interleaved read scheme having a lower number of ways than the number of the interleave groups when the number of defective columns in any of the interleave groups exceeds the number of redundant columns in a respective one of the redundancy interleave groups.

14. A method of reading data from a flash memory device comprising a memory block, wherein the memory block includes a plurality of rows and a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of corresponding redundancy interleave groups of redundant columns, each of the rows comprising a word line and a plurality of the memory cells coupled to the word line, the method comprising:

selecting a row of the memory block;

sequentially latching a first set of data digits from a first interleave group of regular columns in the memory block;

sequentially latching a second set of data digits from a second interleave group of regular columns in the memory block;

latching a data digit from a redundant column in one of the redundancy interleave groups of redundant columns in the memory block, the redundant column being configured to replace a defective column in either the first or second interleave group of regular columns; and

sequentially outputting the latched data digits, wherein sequentially outputting the latched data digits comprises multiplexing the first and second sets of data digits and the data digit from the redundant column,

wherein the method comprises performing one selected from a plurality of interleaved read schemes, based on whether the number of defective columns in each of the interleave groups exceeds the number of redundant columns in a respective one of the redundancy interleave groups.

15. The method of claim 14, further comprising:

receiving a first regular column address indicating a first regular column in the first interleave group; and

selecting the redundant column to retrieve a data digit at least partly in response to the first regular column address.

16. The method of claim 14, further comprising:

receiving a second regular column address indicating a second regular column in the second interleave group; and

selecting the redundant column to retrieve a data digit at least partly in response to the second regular column address.

17. The method of claim 14, further comprising:

sequentially latching a third set of data digits from a third interleave group of regular columns in the memory block; and

sequentially latching a fourth set of data digits from a fourth interleave group of regular columns in the memory block,

wherein the redundant column is configured to replace a defective column in any of the first to fourth interleave groups of regular columns,

wherein sequentially outputting the latched data digits comprises multiplexing the first, second, third, and fourth sets of data digits and the data digit from the redundant column.

18. The method of claim 17, further comprising:

receiving a third regular column address indicating a third regular column in the third interleave group; and

selecting the redundant column to retrieve a data digit at least partly in response to the third regular column address.

19. The method of claim 17, further comprising:

receiving a fourth regular column address indicating a fourth regular column in the fourth interleave group; and

selecting the redundant column to retrieve a data digit at least partly in response to the fourth regular column address.

20. The method of claim 14, wherein the method comprises performing an interleaved read scheme having the same number of ways as the number of the interleave groups when the number of defective columns in each of the interleave groups is equal to or less than the number of redundant columns in a respective one of the redundancy interleave groups.

21. The method of claim 14, wherein the method comprises performing an interleaved read scheme having a lower number of ways than the number of the interleave groups when the number of defective columns in any of the interleave groups exceeds the number of redundant columns in a respective one of the redundancy interleave groups.

22. A method of manufacturing a flash memory device, the method comprising:

providing a flash memory device comprising;

a memory block including a plurality of columns, each of the columns including a bit line and a plurality of memory cells on the bit line, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of redundancy interleave groups of redundant columns;

a plurality of interleave groups of data latches, each of the data latches being configured to store data read from a respective interleave group of regular columns;

a plurality of redundancy interleave groups of redundant data latches, each of the redundant data latches being configured to store data read from a respective redundancy interleave group of redundant columns; and

a multiplexer configured to selectively output data from the plurality of interleave groups of data latches and the plurality of redundancy interleave groups of redundant data latches;

identifying a defective column in each of the interleave groups of regular columns of the flash memory device;

assigning a redundant column in any one of the plurality of groups of redundant columns to replace the identified defective column; and

determining which one of a plurality of different interleaved read schemes is to be used for a read operation of the flash memory device.

23. The method of claim 22, wherein the plurality of interleave groups of columns comprise a first group and a second group, wherein the plurality of redundancy interleave groups of redundant columns comprise a third group and a fourth group, wherein assigning the redundant column comprises assigning a redundant column in the third group to replace a defective column in the first group.

24. The method of claim 23, wherein assigning the redundant column further comprises assigning a redundant column in the fourth group to replace a defective column in the first group.

25. The method of claim 22, wherein the plurality of interleave groups of columns comprise a fifth group and a sixth group, wherein the plurality of redundancy interleave groups of redundant columns comprise a seventh group and an eighth group, wherein assigning the redundant column further comprises assigning a redundant column in the seventh group to replace a defective column in the first group.

26. The method of claim 25, wherein assigning the redundant column further comprises assigning a redundant column in the eighth group to replace a defective column in the first group.

27. The method of claim 22, further comprising determining a number of defective regular columns in each of the interleave groups of regular columns.

28. An apparatus comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of groups of regular columns and a plurality of groups of redundant columns;

a plurality of groups of data latches, each of the groups of data latches being configured to store data read from a respective one group of regular columns;

a plurality of groups of redundant data latches, each of the groups of redundant data latches being configured to store data read from a respective one group of redundant columns; and

a multiplexer configured to selectively output data from the plurality of groups of data latches and the plurality of groups of redundant data latches,

wherein the apparatus is configured to assign a redundant column in one of the groups of redundant columns to replace a defective regular column in any one of the groups of regular columns,

wherein the apparatus further comprises a redundancy selector configured to select a redundant column at least partly in response to the column address of a regular column,

wherein the redundancy selector comprises;

a plurality of column redundancy elements, each of the column redundancy elements being configured to receive the column address of a regular column and a programmed address, the programmed address indicating a defective regular column, and to output a redundancy signal indicative of whether the column address and the programmed address match each other; and

a first logic gate configured to perform an OR operation on the redundancy signals from the plurality of column redundancy elements, and to outputs a redundancy hit signal,

wherein each of the column redundancy element comprises a plurality of second logic gates and a third logic gate, each of the second logic gates being configured to perform an XNOR operation on a respective one bit of the column address and a respective one bit of the programmed address, and to provide an output to the third logic gate, the third logic gate being configured to perform an AND operation on the outputs from the second logic gates, and to output one of the redundancy signals.