Flash memory device with redundant columns
First Claim
1. An apparatus comprising:
- a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of redundancy interleave groups of redundant columns;
a plurality of interleave groups of data latches, each of the interleave groups of data latches being configured to store data read from a respective one interleave group of regular columns;
a plurality of redundancy interleave groups of redundant data latches, each of the redundancy interleave groups of redundant data latches being configured to store data read from a respective one redundancy interleave group of redundant columns; and
a multiplexer configured to selectively output data from the plurality of interleave groups of data latches and the plurality of redundancy interleave groups of redundant data latches,wherein the apparatus is configured to assign a redundant column in one of the redundancy interleave groups of redundant columns to replace a defective regular column in any one of the interleave groups of regular columns;
wherein the apparatus is further configured to allow switching among two or more interleaved read schemes.
8 Assignments
0 Petitions
Accused Products
Abstract
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
-
Citations
28 Claims
-
1. An apparatus comprising:
-
a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of redundancy interleave groups of redundant columns; a plurality of interleave groups of data latches, each of the interleave groups of data latches being configured to store data read from a respective one interleave group of regular columns; a plurality of redundancy interleave groups of redundant data latches, each of the redundancy interleave groups of redundant data latches being configured to store data read from a respective one redundancy interleave group of redundant columns; and a multiplexer configured to selectively output data from the plurality of interleave groups of data latches and the plurality of redundancy interleave groups of redundant data latches, wherein the apparatus is configured to assign a redundant column in one of the redundancy interleave groups of redundant columns to replace a defective regular column in any one of the interleave groups of regular columns; wherein the apparatus is further configured to allow switching among two or more interleaved read schemes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of reading data from a flash memory device comprising a memory block, wherein the memory block includes a plurality of rows and a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of corresponding redundancy interleave groups of redundant columns, each of the rows comprising a word line and a plurality of the memory cells coupled to the word line, the method comprising:
-
selecting a row of the memory block; sequentially latching a first set of data digits from a first interleave group of regular columns in the memory block; sequentially latching a second set of data digits from a second interleave group of regular columns in the memory block; latching a data digit from a redundant column in one of the redundancy interleave groups of redundant columns in the memory block, the redundant column being configured to replace a defective column in either the first or second interleave group of regular columns; and sequentially outputting the latched data digits, wherein sequentially outputting the latched data digits comprises multiplexing the first and second sets of data digits and the data digit from the redundant column, wherein the method comprises performing one selected from a plurality of interleaved read schemes, based on whether the number of defective columns in each of the interleave groups exceeds the number of redundant columns in a respective one of the redundancy interleave groups. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
-
-
22. A method of manufacturing a flash memory device, the method comprising:
-
providing a flash memory device comprising; a memory block including a plurality of columns, each of the columns including a bit line and a plurality of memory cells on the bit line, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of redundancy interleave groups of redundant columns; a plurality of interleave groups of data latches, each of the data latches being configured to store data read from a respective interleave group of regular columns; a plurality of redundancy interleave groups of redundant data latches, each of the redundant data latches being configured to store data read from a respective redundancy interleave group of redundant columns; and a multiplexer configured to selectively output data from the plurality of interleave groups of data latches and the plurality of redundancy interleave groups of redundant data latches; identifying a defective column in each of the interleave groups of regular columns of the flash memory device; assigning a redundant column in any one of the plurality of groups of redundant columns to replace the identified defective column; and determining which one of a plurality of different interleaved read schemes is to be used for a read operation of the flash memory device. - View Dependent Claims (23, 24, 25, 26, 27)
-
-
28. An apparatus comprising:
-
a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of groups of regular columns and a plurality of groups of redundant columns; a plurality of groups of data latches, each of the groups of data latches being configured to store data read from a respective one group of regular columns; a plurality of groups of redundant data latches, each of the groups of redundant data latches being configured to store data read from a respective one group of redundant columns; and a multiplexer configured to selectively output data from the plurality of groups of data latches and the plurality of groups of redundant data latches, wherein the apparatus is configured to assign a redundant column in one of the groups of redundant columns to replace a defective regular column in any one of the groups of regular columns, wherein the apparatus further comprises a redundancy selector configured to select a redundant column at least partly in response to the column address of a regular column, wherein the redundancy selector comprises; a plurality of column redundancy elements, each of the column redundancy elements being configured to receive the column address of a regular column and a programmed address, the programmed address indicating a defective regular column, and to output a redundancy signal indicative of whether the column address and the programmed address match each other; and a first logic gate configured to perform an OR operation on the redundancy signals from the plurality of column redundancy elements, and to outputs a redundancy hit signal, wherein each of the column redundancy element comprises a plurality of second logic gates and a third logic gate, each of the second logic gates being configured to perform an XNOR operation on a respective one bit of the column address and a respective one bit of the programmed address, and to provide an output to the third logic gate, the third logic gate being configured to perform an AND operation on the outputs from the second logic gates, and to output one of the redundancy signals.
-
Specification