Reprogrammable nonvolatile memory devices and methods

• US 7,821,837 B2
• Filed: 05/15/2009
• Issued: 10/26/2010
• Est. Priority Date: 01/31/2006
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chun, Jin-Young, Jeong, Jae-Yong
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US12/466,679
• Publication Number:
  US 20090225603A1
• Time in Patent Office: 529 Days
• Field of Search: 365/185.05, 365/185.11, 365/185.13, 365/185.22, 365/185.29, 365/185.33, 365/185.25
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Claims

1. A nonvolatile memory device comprising:

a memory cell array;

a command decoder configured to generate a reprogram flag signal in response to reprogram command;

a reprogram controller configured to conduct a reprogramming operation on the memory cell array to have threshold voltages equal to or higher than a verifying voltage in response to the reprogram flag signal provided from the command decoder; and

a suspend/resume controller configured to suspend the reprogramming operation in response to a suspend flag signal provided from the command decoder;

wherein the command decoder is configured to generate a resume flag signal in response to termination of a reading/writing operation; and

wherein the suspend/resume controller is configured to resume the reprogramming operation in response to the resume flag signal.

2. The nonvolatile memory device as set forth in claim 1, wherein the command decoder is configured to provide the suspend/resume controller with the suspend flag signal to suspend the reprogramming operation in response to receipt of a read/write command during the reprogramming operation.

3. The nonvolatile memory device as set forth in claim 1, wherein the command decoder is configured to determine, in response to the reprogram command, whether the reading/writing operation is being carried out in the memory cell array.

4. The nonvolatile memory device as set forth in claim 3, wherein, if the reading/writing operation is being carried out when the reprogramming command is received by the command decoder, the command decoder is configured to delay the reprogramming operation until the reading/writing operation is complete.

5. The nonvolatile memory device as set forth in claim 4, wherein the command decoder is configured to provide the reprogram controller with a reprogram flag signal to cause a delayed reprogramming operation to be initiated when the reading/writing operation is complete.

6. The nonvolatile memory device as set forth in claim 1, further comprising:

an address generator configured to generate a reprogram address for the reprogramming operation.

7. The nonvolatile memory device as set forth in claim 6, wherein the address generator is configured to provide the reprogram address to a read/write circuit.

8. The nonvolatile memory device as set forth in claim 7, wherein the reprogram controller is configured to initialize the address generator in response to the reprogram flag signal from the command decoder.

9. The nonvolatile memory device as set forth in claim 8, wherein the address generator is configured to maintain the reprogram address to be used in resuming the suspended reprogramming operation when the reprogramming operation is suspended.

10. The nonvolatile memory device as set forth in claim 1, wherein the command decoder is configured to receive an input information for the reprogramming operation from an external memory controller, a timer and/or a power-on reset circuit.

11. The nonvolatile memory device as set forth in claim 1, further comprising:

a timer configured to generate a reprogram enable signal in response to a passing of a predetermined time for the reprogramming operation.

12. The nonvolatile memory device as set forth in claim 11, wherein the command decoder is configured to provide the reprogram controller with a the reprogram flag signal in response to the reprogram enable signal.

13. The nonvolatile memory device as set forth in claim 1, further comprising:

a power-on reset circuit configured to generate initializing information at a power-on time.

14. The nonvolatile memory device as set forth in claim 13, wherein the command decoder is configured to provide the reprogram controller with a the reprogram flag signal in response to the initializing information.

15. A memory system, comprising:

a memory controller configured to generate a reprogram command indicative of a reprogramming operation and a read/write command indicative of a reading/writing operation; and

a nonvolatile memory device comprising;

a memory cell array;

a command decoder configured to generate a reprogram flag signal in response to reprogram command;

a reprogram controller configured to conduct a reprogramming operation on the memory cell array to have threshold voltages equal to or higher than a verifying voltage in response to the reprogram flag signal provided from the command decoder; and

a suspend/resume controller configured to suspend the reprogramming operation in response to a suspend flag signal provided from the command decoder;

wherein the command decoder is configured to generate a resume flag signal in response to termination of the reading/writing operation; and

wherein the suspend/resume controller is configured to resume the reprogramming operation in response to the resume flag signal.

16. The memory system as set forth in claim 15, wherein the command decoder is configured to provide the suspend/resume controller with the suspend flag signal to suspend the reprogramming operation in response to receipt of the read/write command during the reprogramming operation.

17. A method of operating a nonvolatile memory device, comprising:

receiving a reprogram signal from an external memory controller indicative of a reprogramming operation;

executing the reprogramming operation on memory cells to have threshold voltages equal to or higher than a verifying voltage in response to the reprogram signal;

suspending the reprogramming operation in response to a request for the reading/writing operation during the reprogramming operation; and

automatically resuming the suspended reprogramming operation in response to completion of the reading/writing operation.

18. The method as set forth in claim 17, further comprising:

generating a resume signal internal to the nonvolatile memory device in response to completion of the reading/writing operation;

wherein automatically resuming the reprogramming operation is performed in response to the resume signal.