Adaptive current sense amplifier with direct array access capability

• US 7,821,859 B1
• Filed: 10/09/2007
• Issued: 10/26/2010
• Est. Priority Date: 10/24/2006
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Raghavan, Vijay Kumar Srinivasa
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US11/973,696
• Time in Patent Office: 1,113 Days
• Field of Search: 365/208, 365/207, 365/205, 365/203, 327/51, 327/52
• US Class Current: 365/208
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

A current sense amplifier can include an active load circuit having a first load device and second load device coupled in parallel to a first power supply node. A first load device and second load device can provide an impedance that varies according to a potential at a load control node. A reference current circuit can be coupled between the first load device and a second power supply node that includes a current reference section that provides an impedance according to a bias voltage. A data current circuit can be coupled between the second load device and a plurality of memory cells. An adaptive bias circuit can be coupled between the first power supply and the second power supply node and can include a bias section coupled to the load control node that provides an impedance according to the bias voltage.

Claims

1. A current sense amplifier circuit, comprising:

a reference current leg that includes a reference limit section coupled between a first data node and a bias current node;

a data current leg that includes a data limit section coupled between a second data node and a sense current node; and

an equalization circuit that includes

a first equalization path coupled between the first data node the second data node, and a second equalization path coupled between the bias current node and the sense current node, the first and second equalization paths providing a high or low impedance in response to an equalization signal, and

a first limit section coupled between a first power supply node and the bias current node, and a second limit section coupled between the first power supply node and the data current node;

wherein

a current flowing through the reference limit section, data limit section, first limit section and second limit section is limited according to a limit voltage.

2. The current sense amplifier of claim 1, wherein:

the reference limit section, the data limit section, first limit section, and second limit section each comprise a voltage limit transistor having a gate coupled to receive the limit voltage.

3. The current sense amplifier of claim 2, wherein:

each voltage limit transistor comprises an n-channel insulated gate field effect transistor.

4. The current sense amplifier of claim 1, wherein:

the data current node is coupled to a plurality of nonvolatile memory cells; and

the limit voltage prevents a voltage on the bias current node and the sense current node from exceeding a maximum allowable voltage for the memory cells.

5. The current sense amplifier of claim 1, further including:

a load circuit that provides essentially a same impedance between the first power supply node and the reference current leg and data current leg.

6. The current sense amplifier of claim 5, wherein:

the load circuit includes

a first load transistor coupled between the first power supply node and the first data node, and

a second load transistor coupled between the first power supply node and the second data node having a gate coupled to the gate of the first load transistor.

7. The current sense amplifier of claim 5, wherein:

the reference current leg further includes a reference current generator section that limits a current flowing through the reference current leg to a reference current in response to a bias voltage, the reference current being below the current limit established by the reference limit section;

an adaptive bias current leg that having a bias current section that limits a current flowing through the adaptive bias leg to a bias current in response to the bias voltage; and

the load circuit is coupled to the adaptive bias circuit and the same impedance varies in response to the bias current.

8. The current sense amplifier of claim 7, wherein:

the load circuit comprises

a first load transistor of a first conductivity type coupled between the first power supply node and the first data node, and

a second load transistor of the first conductivity type coupled between the first power supply node and the second data node; and

the reference current generator section comprises a reference transistor of a second conductivity type;

the adaptive bias current leg includes an adaptive load transistor of the first conductivity type having a gate coupled to its drain and the bias current section comprises a bias transistor of the second conductivity type;

wherein

the reference transistor and adaptive load transistors have gates commonly connected to the bias voltage and first load transistor, second load transistor, and adaptive load transistor have commonly connected gates.

9. The current sense amplifier of claim 1, wherein:

the equalization circuit further includes

a first equalization enable device coupled between the first power supply node and the first limit section,

a second equalization enable device coupled between the first power supply node and the second limit section, and

the first and second equalization devices providing high or low impedance paths in response to the equalization signal.

10. The current sense amplifier of claim 1, further including:

a multiplexer (MUX) circuit that selectively couples the data current node between a plurality of memory cells and an input/output node for an integrated circuit containing the current sense amplifier in response to a direct access signal.

11. The current sense amplifier of claim 10, wherein:

the MUX circuit includes an internal node, that is coupled to a second power supply node when the direct access signal has one value, and is coupled to the data current node when the direct access signal has a second value.

12. A current sense amplifier, comprising:

an active load circuit that includes a first load device and second load device coupled in parallel to a first power supply node, the first load device and second load device providing an impedance that varies according to a potential at a load control node;

a reference current circuit coupled between the first load device and a second power supply node that includes a current reference section that provides an impedance according to a bias voltage;

a data current circuit coupled between the second load device and a plurality of memory cells; and

an adaptive bias circuit coupled between the first power supply and the second power supply node that includes a bias section coupled to the load control node that provides an impedance according to the bias voltage.

13. The current sense amplifier of claim 12, wherein:

the first load device and second load device comprise transistors having commonly connected gates;

the current reference section includes a reference transistor having a gate coupled to a reference voltage;

the adaptive bias circuit includes a bias load transistor coupled to the first power supply node and including a gate coupled to its drain and to the gates of the transistors of the first and second load device, and the bias section comprises a bias transistor coupled in series with the bias load transistor having a gate coupled to the reference voltage.

17. The current sense amplifier of claim 12, further including:

a direct access section that includes

a first controllable impedance path coupled between the data current circuit and an internal node,

a second controllable impedance path coupled between the internal node and an external node, and

a third controllable impedance path coupled between the internal node and a second power supply node.

14. The current sense amplifier of 12, further including:

a reference digital to analog converter having an input coupled to receive a reference digital value and an output coupled to provide the reference voltage.

15. The current sense amplifier of 12, further including:

the reference current circuit further includes a reference limit section coupled to a first data node that provides an impedance that varies according to a limit voltage;

the data current circuit includes a data limit section coupled to a second data node that provides an impedance that varies according to the limit voltage; and

a precharge circuit that includes

a first precharge section coupled between the first power supply node and the first data node that provides an impedance according to the limit voltage, and

a second precharge section coupled between the first power supply node and the second data node that provides an impedance according to the limit voltage.

16. The current sense amplifier of claim 15, further including:

a limit digital to analog converter having an input coupled to receive a limit digital value and an output coupled to provide the limit voltage.

18. A method of sensing a data value by comparing a sensed current to a reference current, comprising the steps of:

in a sense mode,

limiting a voltage on the data current node to no more than a maximum voltage limit based on a limit voltage,

limiting a current flow through a reference current leg and a data current leg to no more than a maximum current limit based on a limit voltage,

controlling the current flowing through the reference current leg to value less than the maximum current limit according to a reference voltage, and

varying an impedance of a load circuit coupled to the reference current leg and data current leg according to variations in the current flowing through the reference current leg; and

in a precharge mode, precharging the reference current leg and the data current leg to a potential less than a high power supply level in response to the limit voltage.

19. The method of claim 18, further including:

limiting the voltage on the data current node and the reference current node includes applying the limit voltage to gates of transistors in both the reference current leg and data current leg,

limiting the current flow through the reference current leg and data current leg includes applying the limit voltage to gates of transistors in both the reference current leg and data current leg; and

precharging the reference current leg and the data current leg includes applying the limit voltage to gates of transistors in both a first precharge leg and a second precharge leg, the first precharge leg being coupled to the reference current leg, the second precharge leg being coupled to the data current leg.

20. The method of claim 18, further including:

in a direct access mode, coupling the data current leg to a external input of a semiconductor device by way of an internal node, and

in a standard mode, isolating the data current leg from the external input and coupling the internal node to a power supply node.