Stable temperature adjustment for refresh control

• US 7,821,860 B2
• Filed: 10/16/2006
• Issued: 10/26/2010
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Hiu-Kap, Won, Myung-Gyoo
• Primary Examiner(s): HUR, JUNG H
• Application Number:
  US11/549,889
• Publication Number:
  US 20070121408A1
• Time in Patent Office: 1,471 Days
• Field of Search: 365/193, 365/211, 365/222, 365/233.1, 365/233.11, 365/233.14
• US Class Current: 365/211
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations

Abstract

A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment, a pulse generator may generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized. In other embodiments, the temperature signal may be latched to prevent a transition in the refresh signal during a refresh operation. The temperature signal may be latched in response to one of the clock signals or the refresh signal.

Claims

1. A refresh control circuit comprising:

a counter which generates a plurality of clock signals in response to an oscillator clock signal, the clock signals transitioning between first and second states at respectively different clock periods;

a pulse generator which generates a temperature sensor enable signal in response to the clock signals, wherein the temperature sensor enable signal is in an active state when a clock signal having the longest period among the clock signals is in the first logic state and the rest of the clock signals are in the second logic state, and the temperature sensor enable signal is in an inactive state when the clock signal having the longest period among the clock signals is in the second logic state and when any of the rest of the clock signals is in the first logic state;

a temperature sensor which is enabled to sense a current temperature of a chip and to generate a temperature signal when the temperature sensor enable signal is active, and which is disabled when the temperature sensor enable signal is inactive; and

a refresh master block which selects one of the clock signals in response to the temperature sensor enable signal and the temperature signal, and which generates a refresh signal in response to the selected clock signal.

2. The refresh control circuit of claim 1, wherein the pulse generator comprises:

a synchronizer to synchronize the clock signals based on the clock signal having the longest period among the clock signals; and

a logic unit to generate the temperature sensor enable signal in response to an output of the synchronizer.

3. The refresh control circuit of claim 2, wherein the synchronizer

comprises:

an inverter to receive the clock signal having the longest period among the clock signals; and

a plurality of NAND gates to receive an output of the inverter and at least two of the rest of the clock signals.

4. The refresh control circuit of claim 3, wherein the logic unit comprises:

a NOR gate to receive outputs of the NAND gates; and

an inverter for outputting the temperature sensor enable signal in response to an output of the NOR gate.

5. The refresh control circuit of claim 1, wherein the temperature sensor includes a plurality of temperature trip points and generates the temperature signal corresponding to the temperature trip points according to the sensed temperature of the chip.

6. The refresh control circuit of claim 1, wherein the first logic state comprises a logic low and the second logic state comprises a logic high.

7. A refresh control circuit, comprising:

a counter which generates a plurality of clock signals in response to an oscillator clock signal, the clock signals transitioning between first and second states at respectively different clock periods;

a pulse generator which generates a temperature sensor enable signal in response to the clock signals, wherein the temperature sensor enable signal is in an active state when a clock signal having the longest period among the clock signals is in the first logic state and the rest of the clock signals are in the second logic state, and the temperature sensor enable signal is in an inactive state when the clock signal having the longest period among the clock signals is in the second logic state and when any of the rest of the clock signals is in the first logic state;

a temperature sensor which is enabled to sense a current temperature of a chip and to generate a temperature signal when the temperature sensor enable signal is active, and which is disabled when the temperature sensor enable signal is inactive;

a refresh master block which selects one of the clock signals in response to the temperature sensor enable signal and the temperature signal, and which generates a refresh signal in response to the selected clock signal; and

a logic circuit which synchronizes transitions in the refresh signal to the clock signals to prevent transitions that interfere with a refresh operation.

8. The refresh control circuit of claim 7, wherein the logic circuit is located in the pulse generator.

9. The refresh control circuit of claim 7, wherein the logic circuit comprises a latch circuit to latch and synchronize the temperature signal.

10. The refresh control circuit of claim 7, wherein the first logic state comprises a logic low and the second logic state comprises a logic high.

11. A refresh control method comprising:

generating a plurality of clock signals in response to an oscillator clock signal, the clock signals transitioning between first and second states at respectively different clock periods;

generating a temperature signal corresponding to a current temperature of a chip when a temperature sensor enable signal is in an active state;

generating a refresh signal in response to the plurality of clock signals and the temperature signal; and

synchronizing transitions in the refresh signal to prevent a glitch in the refresh signal;

wherein synchronizing transitions in the refresh signal comprises;

synchronizing the clock signals to generate the temperature sensor enable signal based on a clock signal having the longest period among the clock signals, wherein the temperature sensor enable signal is in the active state when the clock signal having the longest period among the clock signals is in the first logic state and the rest of the clock signals are in the second logic state, and the temperature sensor enable signal is in a non-active state when the clock signal having the longest period among the clock signals is in the second logic state and when any of the rest of the clock signals is in the first logic state.

12. The method of claim 11, further comprising generating a plurality of temperature signals corresponding to a plurality of temperature trip points according to the sensed temperature of the chip.

13. The method of claim 11, wherein the first logic state comprises a logic low and the second logic state comprises a logic high.