Clock data recovery circuit capable of generating clock signal synchronized with data signal

• US 7,822,158 B2
• Filed: 06/30/2006
• Issued: 10/26/2010
• Est. Priority Date: 07/05/2005
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hayakawa, Yasushi, Hirota, Takanori, Ishibashi, Atsuhiko, Ota, Yoshiyuki, Oshita, Takeshi, Ishii, Masashi
• Primary Examiner(s): Torres; Juan A
• Application Number:
  US11/477,597
• Publication Number:
  US 20070018704A1
• Time in Patent Office: 1,579 Days
• Field of Search: 375/354, 370/503, 327/141, 327/165
• US Class Current: 375/354
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Claims

1. A clock data recovery circuit generating an output clock synchronized with a data signal, comprising:

a first detection portion detecting a phase difference between said data signal and said output clock;

a variable delay portion varying a delay of a clock in accordance with a control code; and

a code changing portion changing a value of said control code,

said code changing portion including;

a second detection portion detecting a value of a control code corresponding to a delay equal to one period of said output clock,

a storage portion storing the value of the control code detected by said second detection portion, and

an operation portion adding or subtracting at a time the value stored in said storage portion to/from the control code when a delay amount of said variable delay portion exceeds one period of the clock in synchronizing said output clock with said data signal while changing said control code in accordance with a detection result by said first detection portion.

2. The clock data recovery circuit according to claim 1, wherein

said storage portion includes:

an upper limit value storing portion storing an upper limit value of said control code, and

a lower limit value storing portion storing a lower limit value of said control code,

said operation portion includes

an increment portion generating a code for performing addition/subtraction of the control code in accordance with a detection result by said first detection portion,

a code operating portion performing addition/subtraction of the control code in accordance with the code generated by said increment portion, and

a determination portion determining whether or not the delay amount of said variable delay portion exceeds one period of the clock by determining whether or not the control code computed by said code operating portion attains the upper limit value stored in said upper limit value storing portion or the lower limit value stored in said lower limit value storing portion, and

said code operating portion adds or subtracts at a time the value calculated from the upper limit value stored in said upper limit value storing portion and the lower limit value stored in said lower limit value storing portion, when said determination portion determines that one period of the clock is exceeded.

3. The clock data recovery circuit according to claim 2, wherein said increment portion reduces the delay amount of said variable delay portion in order from a first initial value, when the control code does not reach a delay amount equal to one period of said output clock even when reaching a minimum value, stores the minimum value in said lower limit value storing portion, and increases the delay amount in order from a second initial value to store the control code at a time of being equal to the delay amount of said output clock, into said upper limit value storing portion.

4. The clock data recovery circuit according to claim 2, wherein, in determining whether or not the delay amount of said variable delay portion exceeds one period of the clock, said determination portion adds a prescribed value to the upper limit value stored in said upper limit value storing portion for determination.

5. The clock data recovery circuit according to claim 2, wherein, in determining whether or not the delay amount of said variable delay portion exceeds one period of the clock, said determination portion subtracts a prescribed value from the lower limit value stored in said lower limit value storing portion for determination.

6. The clock data recovery circuit according to claim 2, wherein

said operation portion further includes:

an addition portion adding a prescribed value to the upper limit value stored in said upper limit value storing portion for output to said determination portion, and

a subtraction portion subtracting the prescribed value from the lower limit value stored in said lower limit value storing portion for output to said determination portion,

said determination portion determines whether or not one period of the clock is exceeded based on a value output from said addition portion and a value output from said subtraction portion, and

said code operating portion adds or subtracts a value calculated from the value output from said addition portion, the value output from said subtraction portion, and said prescribed value to/from the control code at a time, when said determination portion determines that one period of the clock is exceeded.

7. The clock data recovery circuit according to claim 1, wherein

said clock data recovery circuit has two said variable delay portions,

said second detection portion detects the control code corresponding to a delay equal to one period of said output clock by controlling a first variable delay portion, and

in synchronizing said output clock with said data signal while changing a control code of a second variable delay portion in accordance with a detection result by said first detection portion, said operation portion adds or subtracts at a time the value stored in said storage portion to/from the control code when a delay amount of said second variable delay portion exceeds one period of the clock.

8. The clock data recovery circuit according to claim 1, wherein said clock data recovery circuit has two said variable delay portions,

said clock data recovery circuit comprising:

a first storage portion storing a control code corresponding to a delay equal to one period of an output clock of a first variable delay portion detected by said second detection portion,

a second storage portion storing a control code corresponding to a delay equal to one period of an output clock of a second variable delay portion detected by said second detection portion,

a comparison portion making a comparison between a value stored in said first storage portion and a value stored in said second storage portion, and

an operation determination portion determining whether or not said clock data recovery circuit is to be operated in accordance with a comparison result by said comparison portion.

9. The clock data recovery circuit according to claim 1, wherein

said clock data recovery circuit has two said variable delay portions,

said second detection portion detects a control code corresponding to a delay equal to one period of said output clock by controlling a first variable delay portion, and

in synchronizing said output clock with said data signal while changing the control code of said first variable delay portion in accordance with a detection result by said first detection portion, when a delay amount of said first variable delay portion exceeds one period of the clock, said operation portion adds or subtracts the value stored in said storage portion to/from the control code of a second variable delay portion at a time, then switches an operation to said second variable delay portion, and thereafter adds or subtracts the value stored in said storage portion to/from the control code of said first variable delay portion at a time for synchronization between said output clock and said data signal, and

in synchronizing said output clock with said data signal while changing the control code of said second variable delay portion in accordance with a detection result by said first detection portion, when a delay amount of said second variable delay portion exceeds one period of the clock, said operation portion adds or subtracts the value stored in said storage portion to/from the control code of said first variable delay portion at a time, then switches an operation to said first variable delay portion, and thereafter adds or subtracts the value stored in said storage portion to/from the control code of said second variable delay portion at a time for synchronization between said output clock and said data signal.

10. The clock data recovery circuit according to claim 1, wherein

said variable delay portion includes:

a plurality of delay circuits,

a plurality of selectors receiving outputs of said plurality of delay circuits, and

a phase interpolation circuit interpolating phases of the clock by controlling outputs of said plurality of selectors, and

a same number of delay circuits and a same number of phase interpolation circuits are connected to each of said plurality of selectors.

11. The clock data recovery circuit according to claim 1, wherein

said variable delay portion includes:

a plurality of delay circuits,

a plurality of selectors receiving outputs of said plurality of delay circuits, and

a phase interpolation circuit interpolating phases of the clock by controlling outputs of said plurality of selectors, and

when said operation portion adds or subtracts the value stored in said storage portion to/from the control code at a time, a value of the control code is changed by switching paths of the selectors and the phase interpolation circuit multiple times.