Receiver, transceiver circuit, signal transmission method, and signal transmission system

• US 7,822,403 B2
• Filed: 06/04/2008
• Issued: 10/26/2010
• Est. Priority Date: 07/14/1999
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka
• Primary Examiner(s): TRINH, TAN H
• Application Number:
  US12/133,092
• Publication Number:
  US 20080242255A1
• Time in Patent Office: 874 Days
• Field of Search: 455/226.1, 455/280, 455/296, 455/227, 455/229, 455/230, 455/231, 455/246.1, 455/256, 455/278.1, 455/289, 455/282, 455/290, 455/291, 455/292, 455/303, 455/333, 455/334, 455/341, 375/346, 341/158, 363/59
• US Class Current: 455/334
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45762 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45986 using switching means, e.g. sample and hold
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Claims

1. A receiver having a plurality of signal lines and a capacitor network having capacitors connected to said signal lines and switches for controlling the connection of said capacitors, wherein:

said receiver includes a common mode voltage elimination circuit for eliminating a common mode voltage present on said plurality of signal lines by connecting at least one of the capacitor nodes containing the component of said common mode voltage to a node held to a specific voltage value.

2. The receiver as claimed in claim 1, wherein said common mode voltage elimination circuit includes a corresponding voltage generating circuit for generating a voltage value corresponding to said common mode voltage, and a capacitor charging circuit for charging one end of said capacitor by the output voltage of said corresponding voltage generating circuit.

3. The receiver as claimed in claim 1, wherein said common mode voltage elimination circuit includes a difference voltage capacitor charging circuit for charging an input capacitor by a difference voltage appearing on said plurality of signal lines, and a connection control circuit for connecting a terminal of said input capacitor to an input terminal of a decision circuit subsequently to a charge period.

4. The receiver as claimed in claim 3, wherein said difference voltage capacitor charging circuit performs the elimination of said common mode voltage simultaneously with a differential to single-ended conversion by connecting one node of said capacitor to a constant voltage.

5. The receiver as claimed in claim 3, wherein said difference voltage capacitor charging circuit couples two nodes of said capacitor respectively to single-ended amplifiers.

6. The receiver as claimed in claim 1, wherein said capacitor network implements PRD.

7. The receiver as claimed in claim 1, wherein said receiver applies feedback for the elimination of said common mode voltage to outputs of two single-ended amplifiers to which signals from said capacitor network are input.

8. The receiver as claimed in claim 1, wherein said capacitor network includes two or more coupling capacitors, and said coupling capacitors are connected in parallel during a precharge period and in series during a decision period.

9. A receiver comprising a plurality of signal lines and a capacitor network having capacitors connected to said signal lines and switches for controlling the connection of said capacitors, wherein

said receiver includes a common mode voltage elimination circuit for eliminating a common mode voltage present on said plurality of signal lines by connecting at least one of capacitor nodes containing the component of said common mode voltage to a node precharged to a specific voltage value.

10. The receiver as claimed in claim 9, wherein said common mode voltage elimination circuit includes a corresponding voltage generating circuit for generating a voltage value corresponding to said common mode voltage, and a capacitor charging circuit for charging one end of said capacitor by the output voltage of said corresponding voltage generating circuit.

11. The receiver as claimed in claim 9, wherein said common mode voltage elimination circuit includes a difference voltage capacitor charging circuit for charging an input capacitor by a difference voltage appearing on said plurality of signal lines, and a connection control circuit for connecting a terminal of said input capacitor to an input terminal of a decision circuit subsequently to a charge period.

12. The receiver as claimed in claim 11, wherein said difference voltage capacitor charging circuit performs the elimination of said common mode voltage simultaneously with a differential to single-ended conversion by connecting one node of said capacitor to a constant voltage.

13. The receiver as claimed in claim 11, wherein said difference voltage capacitor charging circuit couples two nodes of said capacitor respectively to single-ended amplifiers.

14. The receiver as claimed in claim 9, wherein said capacitor network implements PRD.

15. The receiver as claimed in claim 9, wherein said receiver applies feedback for the elimination of said common mode voltage to outputs of two single-ended amplifiers to which signals from said capacitor network are input.

16. The receiver as claimed in claim 9, wherein said capacitor network includes two or more coupling capacitors, and said coupling capacitors are connected in parallel during a precharge period and in series during a decision period.