Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)

• US 7,822,881 B2
• Filed: 10/07/2005
• Issued: 10/26/2010
• Est. Priority Date: 12/27/1996
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Münch, Robert
• Primary Examiner(s): Sorrell; Eron J
• Assistant Examiner(s): Phan; Dean
• Application Number:
  US11/246,617
• Publication Number:
  US 20060031595A1
• Time in Patent Office: 1,845 Days
• Field of Search: None
• US Class Current: 710/8
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Claims

1. A method of processing data in a packet-wise manner using (a) an array of elements configurable with respect to function and interconnection, said array being at least two dimensional and having at least some elements that comprise arithmetic-logic units, and (b) a memory arrangement comprising at least one reading pointer separate from at least one writing pointer, said method comprising the steps of:

processing, with a plurality of said configurable elements, data comprising at least a first packet of data to ascertain a first packet of result data;

writing the first packet of result data into a memory block, said memory block being part of the memory arrangement and said at least one writing pointer being positioned so as to allow writing into a memory area of said memory block; and

subsequent to the processing;

reconfiguring at least one of a first group of at least some of the plurality of said configurable elements, wherein the reconfiguring includes using a configuration data from the memory arrangement, the configuration data being provided only for said first group of at least some of the plurality of said configurable elements, while retaining a configuration of at least one other of the plurality of said configurable elements;

reading out result data of the first packet of result data from the memory after reconfiguration of said at least some of the plurality of said configurable elements in accordance with the position of the reading pointer, said reading pointer being positioned so as to allow reading undisturbed by writing of packet data into said memory arrangement; and

using the reconfigured at least some of the plurality of said configurable elements to process the result data of the first packet of result data in order to obtain second result data.

2. The data-processing method as recited in claim 1, wherein the memory arrangement includes a first memory area and a second memory area, the first and second memory areas being spatially separate, the method further comprising:

in a first configuration;

using the first memory area as a write memory; and

using the second memory area as a read memory; and

subsequent to writing and reading in accordance with the first configuration, reconfiguring the at least some of the plurality of configurable elements to use the first memory area as a read memory and the second memory area as a write memory.

3. The method of claim 1, further comprising:

determining, by a controller and based on a record-type identifier within a data record, whether the data record includes configuration data or a memory control command;

writing, by the controller, at least a portion of the data record to the memory arrangement if the determination is that the data record includes configuration data; and

controlling, by the controller, at least one of the at least one reading pointer and the at least writing pointer in accordance with the data record if the determination is that the data record includes a memory control command.

4. A method of processing data in a packet-wise manner using (a) an array of elements configurable with respect to function and interconnection, said array being at least two dimensional and having at least some elements that comprise arithmetic-logic units, and (b) a memory arrangement comprising at least one reading pointer separate from at least one writing pointer, said method comprising the steps of:

processing, with a plurality of said configurable elements, data comprising at least a first packet of data to ascertain a first packet of result data;

writing the first packet of result data into a memory block, said memory block being part of the memory arrangement and said at least one writing pointer being positioned so as to allow writing into a memory area of said memory block; and

subsequent to the processing;

reconfiguring at least one of a first group of at least some of the plurality of said configurable elements, wherein the reconfiguring includes transferring a configuration data from the memory arrangement to the configurable elements of the first group, the configurable elements being adapted for locally storing the transferred configuration data in respective memory elements, the configuration data being provided only for said first group of at least some of the plurality of said configurable elements, while retaining a configuration of at least one other of the plurality of said configurable elements;

reading out result data of the first packet of result data from the memory after reconfiguration of said at least some of the plurality of said configurable elements in accordance with the position of the reading pointer, said reading pointer being positioned so as to allow reading undisturbed by writing of packet data into said memory arrangement; and

using the reconfigured at least some of the plurality of said configurable elements to process the result data of the first packet of result data in order to obtain second result data.