Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
First Claim
1. A Field Programmable Gate Array integrated circuit comprising:
- a multi-dimensional configurable cell structure including a plurality of configurable cells; and
a configurable interconnect connecting the configurable cells;
wherein each of at least one of the cells is a data processing circuit that is hard-wired within the Field Programmable Gate Array and includes;
at least two input ports, each being at least 4-bit wide;
at least one output port being at least 4-bit wide;
at least one multiplier hardware unit arranged for receiving an input from the at least two input ports and for providing an output to the at least one output port; and
circuitry that couples the at least two input ports and the at least one output port to the configurable interconnect.
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Accused Products
Abstract
A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
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Citations
138 Claims
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1. A Field Programmable Gate Array integrated circuit comprising:
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a multi-dimensional configurable cell structure including a plurality of configurable cells; and a configurable interconnect connecting the configurable cells; wherein each of at least one of the cells is a data processing circuit that is hard-wired within the Field Programmable Gate Array and includes; at least two input ports, each being at least 4-bit wide; at least one output port being at least 4-bit wide; at least one multiplier hardware unit arranged for receiving an input from the at least two input ports and for providing an output to the at least one output port; and circuitry that couples the at least two input ports and the at least one output port to the configurable interconnect. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 39)
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31. A Field Programmable Gate Array integrated circuit comprising:
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a two-dimensional configurable cell structure including a plurality of configurable cells; and a configurable interconnect connecting the configurable cells; wherein each of at least one of the cells is a hard-wired implemented logic circuit arranged for implementing a runtime configurable function and includes; an at least 4-bit wide processing unit configurable in function, each of at least two input ports of the at least 4-bit wide processing unit being at least 4-bit wide and having a respective at least 4-bit wide input register, and each of at least one output port of the at least 4-bit wide processing unit being at least 4-bit wide and having a respective at least one at least 4-bit wide output register; and circuitry that couples the at least two input ports and the at least one output port to the configurable interconnect. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
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58. A configurable data processing cell implemented in an integrated circuit, the integrated circuit being configurable in function at runtime and having (a) a multi-dimensionally arranged configurable cell structure and (b) a configurable interconnect connecting configurable cells of the configurable cell structure, wherein the data processing cell is hard-wired implemented in the cell structure, the data processing cell comprising:
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at least one adder hardware unit; at least one multiplier hardware unit; at least two input ports, each being at least 4-bit wide, the at least two input ports being arranged for providing input to the at least one adder and at least one multiplier; at least one output port being at least 4-bit wide, the at least one multiplier being arranged for providing an output to the at least one output port; and circuitry that couples the at least two input ports and the at least one output port to the configurable interconnect; wherein at least one of the input ports is arranged such that a function of the data processing cell is definable by the at least one of the input ports independently from other cells at runtime. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83)
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84. A configurable data processing cell implemented in an integrated circuit, the integrated circuit being configurable in function at runtime and having (a) a multi-dimensionally arranged configurable cell structure and (b) a configurable interconnect connecting the configurable cells, wherein the configurable data processing cell is hard-wired implemented in the cell structure, the configurable data processing cell comprising:
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at least three inputs, each being at least 4-bit wide; at least one output being at least 4-bit wide; at least one adder function unit; at least one multiplier function unit; and at least one of (a) at least one arithmetic function unit and (b) at least one logic function unit; wherein individual ones of the function units are selectively interconnectable such that an output of at least one of the at least one adder function unit, the at least one multiplier function unit, and the at least one of (a) at least one arithmetic function unit and (b) at least one logic function unit is selectively used as an input to another of the at least one adder function unit, the at least one multiplier function unit, and the at least one of (a) at least one arithmetic function unit and (b) at least one logic function unit. - View Dependent Claims (85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110)
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111. A configurable data processing cell implemented in an integrated circuit, the integrated circuit being configurable in function and interconnection at runtime and having (a) a multi-dimensionally arranged configurable cell structure and (b) a configurable interconnect connecting the configurable cells, wherein the data processing cell is hard-wired implemented in the cell structure, the data processing cell comprising:
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at least two input registers; at least one output register; and at least one hard-wired floating point unit arranged for receiving an input from the at least two input registers and providing an output to the at least one output register. - View Dependent Claims (112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124)
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125. A data processor integrated circuit that is configurable in function at runtime, comprising:
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configurable elements arranged in a two-dimensional manner; and a configurable interconnect for connecting the configurable elements in a configurable manner; wherein each of at least some of the configurable elements comprises; at least one ALU (a) being at least 4-bit wide, (b) having a set of predefined, non-alterable instructions, and (c) and including circuitry via which to execute arithmetic logic operations in accordance with said set of predefined, non-alterable instructions; at least two input registers, each being at least 4-bit wide and including circuitry in which operands received over the configurable interconnect are storable; at least one at least 4-bit wide output register for storing result data produced by the at least one ALU in accordance with the configuration information; at least one at least 4-bit wide multiplexer located between at least one of the input registers and at least one input of the at least one ALU, at least one of the at least two input registers being connected to at least a first input of the at least one multiplexer. - View Dependent Claims (126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138)
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Specification