Apparatus and method for protecting diagnostic ports of secure devices

• US 7,822,995 B2
• Filed: 03/03/2005
• Issued: 10/26/2010
• Est. Priority Date: 03/03/2005
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Hars, Laszlo, Beaver, Donald Rozinak
• Primary Examiner(s): Moazzami; Nasser
• Assistant Examiner(s): Traore; Fatoumata
• Application Number:
  US11/070,911
• Publication Number:
  US 20060200682A1
• Time in Patent Office: 2,063 Days
• Field of Search: None
• US Class Current: 713/193
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 21/62 Protecting access to data via a platform, e.g. using keys or access control rules
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen

Abstract

An electronic system comprises a processor, a diagnostic port, and a switching circuit, including a switch connected between the diagnostic port and the processor, for enabling and disabling the diagnostic port and for restricting access to contents of the electronic system prior to enabling the diagnostic port. A method for operating the electronic system is also included.

Claims

1. An electronic system comprising:

a processor;

a diagnostic port;

a switching circuit, including a switch connected between the diagnostic port and the processor, for enabling and disabling the diagnostic port and for restricting access to contents of the electronic system prior to enabling the diagnostic port;

a hardware sensor circuit for detecting if a connector is attached to the diagnostic port and for activating the switching circuit if the connector is detected; and

a secret root key stored in a non-volatile memory for encrypting and decrypting data in the electronic system, wherein the switching circuit restricts access to contents of the electronic system by masking the secret root key such that attempted access to the secret root key results in a predetermined value, and wherein the switching circuit resets the system before the switch is closed.

2. The electronic system of claim 1, wherein the switching circuit further comprises:

a multiplexer, wherein the switching circuit controls the operation of the multiplexer to alternatively enable or block the secret root key.

3. The electronic system of claim 1, wherein the switching circuit periodically checks the operational status of the switch.

4. The electronic system of claim 1, wherein resetting the system includes erasing memory.

5. The electronic system of claim 1, further comprising:

a tamper indicating device for indicating that the diagnostic port has been used.

6. The electronic system of claim 1, wherein the switching circuit closes the switch after the system has been reset.

7. The electronic system of claim 1, further comprising:

one or more user keys, generated by using the secret root key, for encrypting and decrypting data in the electronic system.

8. A method of operating an electronic system, the method comprising:

providing a switching circuit, including a switch connected between a diagnostic port and a processor for enabling and disabling the diagnostic port;

determining the operational status of the switch;

using a hardware sensing circuit to detect if a connector is attached to the diagnostic port and to activate the switching circuit if the connector is detected; and

using the switching circuit to restrict access to contents of the electronic system in response to the operational status of the switch prior to enabling the diagnostic port, wherein the switching circuit restricts access to contents of the electronic system by masking a secret root key such that attempted access to the secret root key results in a predetermined value, and wherein the switching circuit resets the system before the switch is closed.

9. The method of claim 8, wherein the switching circuit restricts access to contents of the electronic system by erasing memory.

10. The method of claim 8, wherein the switching circuit restricts access to contents of the electronic system by erasure or reset of a subset of memory.

11. The method of claim 8, wherein the switching circuit restricts access to contents of volatile memory of the electronic system by encrypting the volatile memory contents prior to erasing the volatile memory.

12. The method of claim 8, wherein the switching circuit periodically checks the operational status of the switch.

13. The method of claim 8, wherein resetting the system includes erasing memory.