Memory hub tester interface and method for use thereof
First Claim
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1. A memory hub, comprising:
- a memory test bridge circuit having a tester interface through which test command packets are received responsive to a test clock signal and further having a memory interface coupled to the tester interface through which memory commands corresponding to a test command packet are provided to at least one memory device responsive to a memory clock signal; and
an error detect circuit coupled to the memory test bridge circuit for comparing expected data received by the memory test bridge circuit to read data returned from the memory device in response to a memory command, the error detect circuit operable to generate in response to the comparison pass/fail data indicative of whether the read data matches the expected data.
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Abstract
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command, address, and data signals in accordance with the test command packets, and the memory device command, address, and data signals are provided to a memory device under test that is coupled to the memory hub responsive to a memory device clock signal having a memory device clock frequency.
281 Citations
24 Claims
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1. A memory hub, comprising:
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a memory test bridge circuit having a tester interface through which test command packets are received responsive to a test clock signal and further having a memory interface coupled to the tester interface through which memory commands corresponding to a test command packet are provided to at least one memory device responsive to a memory clock signal; and an error detect circuit coupled to the memory test bridge circuit for comparing expected data received by the memory test bridge circuit to read data returned from the memory device in response to a memory command, the error detect circuit operable to generate in response to the comparison pass/fail data indicative of whether the read data matches the expected data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory module, comprising:
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a plurality of memory devices; a memory device bus coupled to the memory devices; and a memory hub coupled to the memory device bus, the memory hub comprising; a memory test bridge circuit having a tester interface through which test command packets are received responsive to a test clock signal and further having a memory interface coupled to the tester interface through which memory commands corresponding to a test command packet are provided to at least one memory device responsive to a memory clock signal; and an error detect circuit coupled to the memory test bridge circuit for comparing expected data received by the memory test bridge circuit to read data returned from the memory device in response to a memory command, the error detect circuit operable to generate in response to the comparison pass/fail data indicative of whether the read data matches the expected data. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for testing a memory device, comprising:
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coupling test command packets from a tester to a memory hub responsive to a test clock signal having a test clock frequency; generating in the memory hub memory device command, address, and data signals in accordance with the test command packets; and coupling the memory device command, address, and data signals from the memory hub to a memory device under test responsive to a memory device clock signal having a memory device clock frequency. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method for testing a memory device, comprising:
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providing test command packets to a memory hub in parallel for testing a memory device under test; and for each command packet provided to the memory hub in parallel, generating in the memory hub memory device command, address, and data signals in accordance with the selected test command packet and providing the memory device command, address, and data signals to the memory device under test at a rate faster than which the test command packets are provided to the memory hub in parallel. - View Dependent Claims (22, 23, 24)
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Specification