Data processing with configurable registers

• US 7,823,033 B2
• Filed: 07/26/2006
• Issued: 10/26/2010
• Est. Priority Date: 07/26/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gumulja, Jimmy, Moyer, William C.
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US11/460,090
• Publication Number:
  US 20080126769A1
• Time in Patent Office: 1,553 Days
• Field of Search: None
• US Class Current: 714/724
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag

Abstract

A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user'"'"'s programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.

Claims

1. In a data processing system, a method comprising:

providing a plurality of general purpose registers (GPRs) which are included as part of a user'"'"'s programming model for the data processing system;

entering a test mode;

during the test mode, configuring a portion of the plurality of general purpose registers to operate as at least one multiple input shift register (MISR) wherein a portion of a register line is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation;

during the test mode, each register in the portion of the plurality of general purpose registers generating a signature;

exiting the test mode; and

after exiting the test mode, using the portion of the plurality of general purpose registers as general purpose registers for normal program execution.

2. The method of claim 1, wherein the configuring the portion of the plurality of general purpose registers to operate as at least one MISR comprises:

implementing one or more bit cells of each register in the portion of the plurality of general purpose registers with at least one logic gate wherein, during the test mode, the at least one logic gate receives a first input from another bit cell and the at least one logic gate provides an output to yet another bit cell; and

providing test data from test points located at predetermined circuit nodes within the data processing system to a second input of the at least one logic gate.

3. The method of claim 1, wherein the portion of the plurality of general purpose registers correspond to a selected subset of registers of the plurality of general purpose registers.

4. The method system of claim 3, wherein the selected subset of registers is selected based on a software Application Binary Interface (ABI).

5. The method of claim 1, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.

6. The method of claim 5, wherein remaining bit locations within each register of the selected subset of registers of the plurality of general purpose registers continue to operate as general purpose registers for normal program execution during the test mode.

7. The method of claim 5, wherein the subset of bit locations corresponds to higher order bit locations within the each register of the selected subset of registers of the plurality of general purpose registers.

8. The method of claim 1, further comprising:

during test mode, using at least one register in the portion of general purpose registers configured as the at least one MISR as a source register for a processor instruction executed by the data processing system.

9. The method of claim 8, wherein the processor instruction performs an operation selected from a group consisting of an arithmetic operation, a logic operation, or an effective address calculation.

10. A data processing system, comprising:

functional circuitry which performs at least one data processing function;

a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user'"'"'s programming model for the data processing system, wherein a portion of the plurality of general purpose registers are reconfigurable as at least one test register during a test mode, a portion of a register line of the at least one test register is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation; and

control circuitry which provides a test enable indicator to the register file, wherein the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operate to accumulate test data from predetermined circuit nodes within the functional circuitry.

11. The data processing system of claim 10, wherein the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from the predetermined circuit nodes within the functional circuitry and generate a signature used to test functionality of the functional circuitry.

12. The data processing system of claim 10, wherein the at least one test register comprises at least one multiple input shift register (MISR).

13. The data processing system of claim 10, wherein the register file further comprises:

selecting circuitry coupled to storage circuitry in each register of the portion of the plurality of GPRs, the selecting circuitry selecting between providing a normal write input to the storage circuitry and providing a test input based at least in part on the test enable indicator.

14. The data processing system of claim 13, wherein the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled.

15. The data processing system of claim 10, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.

16. The data processing system of claim 15, wherein remaining bit locations within each register of the selected subset of registers of the plurality of general purpose registers continue to operate as general purpose registers for normal program execution during the test mode.

17. A data processing system, comprising:

functional circuitry which performs at least one data processing function;

a register file having a plurality of general purpose registers (GPRs) which are included as part of a user'"'"'s programming model for the data processing system, wherein a portion of the plurality of general purpose registers are reconfigurable as at least one multiple input shift register (MISR) during a test mode, a portion of a register line of the plurality of general purpose registers is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation; and

control circuitry which provides a test enable indicator to the register file, wherein each register in the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operates as at least a portion of a multiple input shift register (MISR) to generate a signature based on test data received from predetermined circuit nodes within the functional circuitry.

18. The data processing system of claim 17, wherein the register file comprises:

selecting circuitry for each bit cell in each register of the portion of the plurality of general purpose registers, the selecting circuitry selecting between providing a normal write input and providing a test input based at least in part on the test data received from the predetermined circuit nodes within the functional circuitry; and

a logic gate in each bit cell in each register of the portion of the plurality of general purpose registers, each logic gate coupled to receive at least a portion of the test data from the predetermined circuit nodes within the functional circuitry and coupled to provide the test input to the selecting circuitry.

19. The data processing system of claim 18, wherein the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled.

20. The data processing system of claim 17, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.