Automatic integrated circuit routing using spines

• US 7,823,113 B1
• Filed: 09/11/2006
• Issued: 10/26/2010
• Est. Priority Date: 06/07/2004
• Status: Active Grant

• Current Assignee: Pulsic Limited
• Original Assignee: Pulsic Limited
• Inventors: Sato, Fumiako, Williams, Mark, Balsdon, Graham, Waller, Mark, Birch, Jeremy, Parker, Tim
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Parihar; Suchin
• Application Number:
  US11/530,613
• Time in Patent Office: 1,506 Days
• Field of Search: 716/1, 716/12
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.

Claims

1. A method comprising:

providing a gridless routing area, wherein the route area has a rectangular shape and is bounded by a first, second, third, and fourth side, the third side is opposite of the first side, the fourth side is opposite of the second side, the first side is longer than the second side, the first and third sides extend in a first direction, the second and fourth sides extend in a second direction, and the second direction is orthogonal to the first direction, and a plurality of first pins, to be coupled together using a first interconnect, at the first or third side of the routing area and a plurality of second pins, to be coupled together using a second interconnect, at the first or third side of the routing area;

by a computer, generating within the gridless routing area, a first spine polygon of the first interconnect having a plurality of straight edges extending in the first direction a length from the second side to the fourth side of the routing area and a uniform first width between the straight edges;

by the computer, generating within the gridless routing area, a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending in the first direction a length from the second side to the fourth side of the routing area and the uniform first width between the straight edges, wherein between the first and second spine polygons is a space, extending parallel to the first and second polygons;

after generating the first and second spine polygons, generating a first plurality of stitch polygons to couple each of the first pins to the first polygon, a first stitch polygon and a second stitch polygon of the first plurality of stitch polygons forming first and second T-junctions with the first polygon; and

after generating the first and second spine polygons, generating a second plurality of stitch polygons to couple each of the second pins to the second polygon, a third stitch polygon and a fourth stitch polygon of the second plurality of stitch polygons forming third and fourth T-junctions with the second polygon.

2. The method of claim 1 wherein a length-to-width ratio of the routing area is at least four-to-one.

3. The method of claim 1 wherein at least one of the stitch polygons has a length greater than its width, and its length is perpendicular to the length of the spine polygons.

4. The method of claim 1 wherein the gridless routing area comprises an obstacle polygon and generating a first plurality of stitch polygons to couple each of the first pins to the first polygon comprises:

performing one or more flood operations to route at least one of the stitch polygons around the obstacle.

5. The method of claim 1 further comprising:

providing a forbidden area within the gridless routing area, wherein the first and second spine polygons are positioned within the gridless routing area and outside the forbidden area.

6. The method of claim 1 further comprising:

automatically routing at least one shield interconnect parallel to the first interconnect on a different layer than the first interconnect.

7. The method of claim 1 further comprising:

automatically routing a plurality of shield interconnects parallel to the first interconnect on different layers than the first interconnect.

8. The method of claim 7 further comprising automatically routing two shield interconnects disposed on opposite dies of the first interconnect on the same layer as the first interconnect.

9. The method of claim 1 further comprising:

generating a fifth stitch polygon to couple a third pin of the routing area to the first spine polygon, wherein the fifth stitch polygon forms a first L-junction with the first spine polygon;

generating a sixth stitch polygon to couple a fourth pin of the routing area to the first spine polygon, wherein the sixth stitch polygon forms a second L-junction with the first spine polygon and the first and second T-junctions are between the first and second L-junctions.

10. A method comprising:

providing a rectangular routing area having a length L at least four times greater than a width;

providing at least a first pin and a second pin along a first length side of the routing area, and at least a third pin and a fourth pin along a second length side of the routing area, wherein the first and third pins are to be coupled together using a first interconnect, and the second and fourth pins are to be coupled together using a second interconnect;

by a computer, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length L of the routing area and a uniform spine width between the straight edges;

by a computer, within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length L of the routing area and the uniform spine width between the straight edges;

generating a first plurality of stitch polygons to couple the first and third pins to the first polygon;

generating a second plurality of stitch polygons to couple the second and fourth pins to the second polygon;

providing fifth pin along the first length side and a sixth pin along the second length side, wherein the fifth pin is to be coupled together with the first and third pins using the first interconnect, and the sixth pin is to be coupled together with the second and fourth pins using the second interconnect, and

the generating a first plurality of stitch polygons comprises generating a stitch polygon to couple the fifth pin to the first spine polygon, and

the generating a second plurality of stitch polygons comprises generating a stitch polygon to couple the sixth pin to the second spine polygon.

11. The method of claim 10 wherein each stitch polygon of the first and second plurality of stitch polygons has a length greater than its width, and its length is perpendicular to the length of the routing area.

12. The method of claim 10 wherein the routing area is gridless.

13. The method of claim 10 wherein the routing area comprises an obstacle polygon and the generating a first plurality of stitch polygons to couple the first and third pins to the first spine polygon comprises finding a path for the stitch polygons which does not pass through the obstacle polygon.

14. The method of claim 10 further comprising:

designating a forbidden area within the routing area, wherein the generating a first spine polygon of the first interconnect and generating a second spine polygon avoids placing the first and second spine polygons in the forbidden area.

15. The method of claim 10 wherein the first and second spine polygons are on are first layout layer, and the first and second plurality of stitch polygons are on a second layout layer, different than the first layout layer.

16. A method comprising:

providing a rectangular routing area having a length L at least four times greater than a width;

providing at least a first pin and a second pin along a first length side of the routing area, and at least a third pin and a fourth pin along a second length side of the routing area, wherein the first and second pins are to be coupled together using a first interconnect, and the third and fourth pins are to be coupled together using a second interconnect;

within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length L of the routing area and a uniform spine width between the straight edges;

within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length L of the routing area and the uniform spine width between the straight edges;

by a computer, generating a first plurality of stitch polygons to couple the first and second pins to the first polygon, a first stitch polygon forming a forming first T-junction with the first polygon and a second stitch polygon forming second T-junction with the first polygon; and

by a computer, generating a second plurality of stitch polygons to couple the third and fourth pins to the second polygon, a third stitch polygon forming a third T-junction with the second polygon and a fourth stitch polygon forming fourth T-junction with the second polygon.

17. The method of claim 16 further comprising:

providing fifth pin along the second length side, wherein the fifth pin is to be coupled together with the first and second pins using the first interconnect, and

the generating a first plurality of stitch polygons comprises generating a fifth stitch polygon to couple the fifth pin to the first spine polygon, wherein the fifth stitch polygon forms an L-junction with the first spine polygon.

18. The method of claim 16 wherein the routing area comprises an obstacle polygon and the generating a first plurality of stitch polygons to couple the first and second pins to the first spine polygon comprises finding a path for the stitch polygons which does not pass through the obstacle polygon.

19. The method of claim 16 further comprising:

designating a forbidden area within the routing area, wherein the generating a first spine polygon of the first interconnect and generating a second spine polygon avoids placing the first and second spine polygons in the forbidden area.

20. The method of claim 16 wherein the first and second spine polygons are on are first layout layer, and the first and second plurality of stitch polygons are on a second layout layer, different than the first layout layer.