Stacked imager package
First Claim
1. A method of interconnecting chips in a chip package, comprising:
- forming backside metallurgy on a first chip;
connecting said backside metallurgy on said first chip to pads on an active surface of said first chip by conductors extending from said backside metallurgy to said pads; and
connecting metallurgy on an active surface of a second chip to said backside metallurgy by an array of interchip solder bumps.
3 Assignments
0 Petitions
Accused Products
Abstract
An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
12 Citations
11 Claims
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1. A method of interconnecting chips in a chip package, comprising:
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forming backside metallurgy on a first chip; connecting said backside metallurgy on said first chip to pads on an active surface of said first chip by conductors extending from said backside metallurgy to said pads; and connecting metallurgy on an active surface of a second chip to said backside metallurgy by an array of interchip solder bumps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification