LDMOS using a combination of enhanced dielectric stress layer and dummy gates

• US 7,824,968 B2
• Filed: 07/17/2006
• Issued: 11/02/2010
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Chu, Sanford, Verma, Purakh Raj, Li, Yisuo, Zhang, Guowei
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US11/488,117
• Publication Number:
  US 20080014690A1
• Time in Patent Office: 1,569 Days
• Field of Search: 438/197, 438/135, 438/301, 438/303, 438/307, 257/E21.433
• US Class Current: 438/135
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

Claims

1. A method of fabrication of a semiconductor transistor comprising the steps of:

providing a substrate with a deep well having dopants of a second dopant type;

forming a gate over the substrate, the gate having first and second sides and a channel under the gate;

forming a first junction region in the substrate on the first side of the gate, the first junction region having dopants of a first dopant type with a first dopant concentration;

forming a second junction region in the substrate on a second side of the gate adjacent the channel, the second junction region having dopants of the first type with a second dopant concentration, wherein the deep well comprises a depth deeper than the first and second junction regions, the deep well encompassing the first junction region and overlaps a portion of the second junction region without encompassing the second junction;

forming a third junction region in the substrate adjacent the second junction region and spaced apart from the second side of the gate, the third junction region having dopants of the first type with a third dopant concentration, the second dopant concentration of the second junction region is less than the first and third dopant concentration of the first and third junction regions;

forming at least one dummy gate over the second junction region; and

forming a stress layer over the substrate and over the gate and at least one dummy gate, the stress layer creates a stress in the channel and in the second junction region, wherein the dummy gate is arranged to assist in distributing the stress of the stress layer over the second and third junctions to increase the stress exerted across the second junction region as compared to that without the at least one dummy gate to improve performance of the transistor.

2. The method of claim 1, further wherein the semiconductor transistor is a LDMOS, P LDMOS, N LDMOS, RF LDMOS, HV FET, HV FET SOI, high voltage field effect transistor, or a field effect transistor having an offset source and/or offset drain.

3. The method of claim 1, further comprising the steps of:

forming a dielectric layer over the substrate wherein the gate is formed over the dielectric layer;

forming an inter-level dielectric (ILD) layer over the stress layer;

patterning the ILD layer to expose;

i) a portion of the substrate within the first junction region;

ii) a portion of the gate; and

iii) a portion of the substrate within the second junction region; and

forming respective contacts within the patterned ILD layer at the exposed first junction region, the exposed gate and the exposed second junction region.

4. The method of claim 1, wherein the first, second and third junction regions are N-type and the stress layer is a tensile stress layer that exerts a tensile stress on the channel and a tensile stress on the second junction region.

5. The method of claim 1, wherein the first, second and third junction regions are P-type and the stress layer is a compressive stress layer that exerts a compressive stress on the channel and a compressive stress on the second junction region.

6. The method of claim 1, wherein the ratio of the length of the second junction region to the length of the channel is from about 1 to 20.

7. The method of claim 1, wherein the dummy gate does not increase the stress in the channel.

8. The method of claim 1 which further comprises:

the first junction region is a source region;

said second junction region is an offset drain region;

said third region is a drain region;

forming a fourth junction region in the substrate adjacent the source region and adjacent the first side of the gate;

said fourth region is a offset source region;

the fourth junction region has a fourth dopant concentration;

the fourth dopant concentration of the fourth junction region is less than the first dopant concentration of the source region.

9. The method of claim 1, wherein the stress layer creating a stress in the channel and the second junction region that is from about 1 Mpa and 3 Gpa.

10. The method of claim 1, wherein the first junction region is adjacent the first side of the gate.

11. A method of fabrication of a metal-oxide-semiconductor device;

comprising the steps of;

providing a substrate with a deep well having dopants of a second dopant type;

forming a gate over the substrate, the gate having first and second sides and a channel under the gate;

forming a source in the substrate proximate the first side of the gate;

the source having dopants of a first dopant type with a first dopant concentration;

forming a body sinker in the substrate spaced apart from the first side of the gate;

forming an offset drain region in the substrate adjacent the second side of the gate;

the offset drain region having dopants of the first type with a second dopant concentration, wherein the deep well comprises a depth deeper than the source and offset drain regions, the deep well encompassing the source and overlaps a portion of the offset drain region without encompassing the offset drain region;

forming a drain in the substrate adjacent the offset drain region and spaced apart from the second side of the gate, the drain having dopants of the first type with a third dopant concentration, the second dopant concentration of the offset drain being less than the first and third dopant concentration of the source and drain;

forming at least one dummy gate over the offset drain region; and

forming a stress layer over the substrate and over the gate and the at least one dummy gate, wherein the dummy gate is arranged to assist in distributing the stress of the stress layer over the offset drain region and the drain to increase the stress exerted across the offset drain region as compared to that without the at least one dummy gate to improve performance of the device.

12. The method of claim 11, further comprising the step of forming a offset source in the substrate adjacent the gate and the source region:

and forming the stress layer over said offset source region.

13. The method of claim 11, further comprising the steps of:

forming an inter-level dielectric (ILD) layer over the stress layer;

patterning the ILD layer to expose;

i) a portion of the substrate within the source;

ii) a portion of the gate; and

iii) a portion of the substrate within the offset drain; and

forming respective contacts within the patterned ILD layer at the exposed source, the exposed gate and the exposed offset drain;

the stress layer creating a stress in the channel and in the offset drain of from about 3 Mpa and 3 Gpa; and

the ratio of the length of the offset drain to the length of the channel being from about 1 to 20.

14. The method of claim 11, wherein the source, offset drain and drain are N-type and the stress layer is a tensile stress layer that exerts a tensile stress on the channel and a tensile stress on the offset drain.

15. The method of claim 11, wherein the source, offset drain and drain are P-type and the stress layer is a compressive stress layer that exerts a compressive stress on the channel and a compressive stress on the offset drain.

16. The method of claim 11, further comprising the step of forming an offset source in the substrate between the gate and the source region:

and

forming a dummy gate over said offset source region; and

forming the stress layer over the dummy gate.

17. The method of claim 11 wherein the dummy gate assists in distributing the stress of the stress layer over the offset drain region but does not increase the stress in the channel.

18. A method of fabricating a semiconductor device comprises:

providing a substrate with a deep well having dopants of a second dopant type;

forming a transistor gate over a surface of the substrate with a channel beneath the gate;

forming a first junction region in the substrate on a first side of the gate, the first junction region having dopants of a first dopant type with a first dopant concentration;

forming a second junction region in the substrate on a second side of the gate adjacent to the channel, the second junction region having dopants of the first type with a second dopant concentration, wherein the deep well comprises a depth deeper than the first and second junction regions, the deep well encompassing the first junction region and overlaps a portion of the second junction region without encompassing the second junction;

forming at least one dummy gate over the substrate within the second junction region; and

forming a stress layer over the substrate and over the gate and the at least one of the dummy gate, wherein the stress layer provides a first type stress in the channel and in the second junction region, wherein the dummy gate is arranged to assist in distributing the stress of the stress layer over the second junction to increase the stress exerted across the second junction region as compared to that without the at least one dummy gate to improve performance of the device.

19. The method of claim 18, wherein the at least one dummy gate having the stress layer disposed thereover assists in distributing the stress over the second junction region but does not increase the stress in the channel.

20. The method of claim 18 wherein:

the transistor comprises a n-type transistor and the first type stress comprises a tensile stress;

or

the transistor comprises a p-type transistor and the first type stress comprises a compressive stress.

21. A method of forming a device comprising:

providing a substrate with a deep well having dopants of a second dopant type, wherein the device region is prepared with

a gate on the substrate with a channel region below the gate,

a first junction region adjacent to and on a first side of the gate, the first junction region comprising a first dopant type having a first dopant concentration,

a second junction region adjacent to and on a second side of the gate, the second junction region comprising the first dopant type having a second dopant concentration which is lower than the first dopant concentration, wherein the deep well comprises a depth deeper than the first and second junction regions, the deep well encompassing the first junction region and overlaps a portion of the second junction region without encompassing the second junction,

a third junction region adjacent on the second side of the gate and separated from the gate by the second junction region, wherein the third junction region comprises the first dopant type having a third dopant concentration which is greater than the second dopant concentration, and

at least one dummy gate disposed on the substrate over the second junction region; and

forming a stress layer over the substrate and the at least one dummy gate, the stress layer exerts a stress in the channel, wherein the at least one dummy gate is arranged to assist in distributing the stress of the stress layer over the second and third junctions to increase the stress exerted across the second junction region as compared to that without the at least one dummy gate to improve performance of the device.

22. The method of claim 21 wherein the at least one dummy gate comprises a non-electrically functional dummy gate.

23. The method of claim 22 wherein:

the first junction comprises a source junction;

the second junction comprises an offset drain junction; and

the third junction comprises a drain junction.

24. The method of claim 22 wherein the device comprises a LDMOS or HV FET.

25. The method of claim 22 wherein the gate and the at least one dummy gates are formed in the same process.

26. The method of claim 22 wherein:

the first dopant type comprises p-type and the stress comprises a compressive stress;

or

the first dopant type comprises n-type; and

the stress comprises a tensile stress.

27. The method of claim 22 comprises a plurality of dummy gates.

28. The method of claim 22 wherein the gate and the at least one dummy gate have exposed sidewalls prior to forming the stress layer.

29. The method of claim 22 wherein:

the first dopant concentration is about 5E19 to 2E21 atoms/cc;

the second dopant concentration is about 1E16 to 1E18 atoms/cc; and

the third dopant concentration is about 5E19 to 2E21 atoms/cc.

30. The method of claim 22 wherein the device region comprises a doped well having dopants of a second type.

31. The method of claim 22 wherein the stress exerted on the second junction region is increased by 1-100%.

32. The method of claim 22 wherein increasing the stress exerted on the second junction region reduces Ron of the device.

33. The method of claim 22 wherein a ratio of a length of the channel and second junction region is about 1-20.

34. The method of claim 21 wherein:

the first junction comprises a source junction;

the second junction comprises an offset drain junction; and

the third junction comprises a drain junction.

35. The method of claim 21 wherein the device comprises a LDMOS or HV FET.

36. The method of claim 21 wherein the gate and the at least one dummy gates are formed in the same process.

37. The method of claim 21 wherein:

the first dopant type comprises p-type and the stress comprises a compressive stress;

or

the first dopant type comprises n-type; and

the stress comprises a tensile stress.

38. The method of claim 21 comprises a plurality of dummy gates.

39. The method of claim 21 wherein the gate and the at least one dummy gate have exposed sidewalls prior to forming the stress layer.

40. The method claim 21 wherein:

the first dopant concentration is about 5E19 to 2E21 atoms/cc;

the second dopant concentration is about 1E16 to 1E18 atoms/cc; and

the third dopant concentration is about 5E19 to 2E21 atoms/cc.

41. The method of claim 21 wherein the device region comprises a doped well having dopants of a second type.

42. The method of claim 21 wherein the stress exerted on the second junction region is increased by 1-100%.

43. The method of claim 21 wherein increasing the stress exerted on the second junction region reduces Ron of the device.

44. The method of claim 21 wherein a ratio of a length of the channel and second junction region is about 1-20.