Producing a thin film transistor substrate by using a photoresist pattern having regions of different thicknesses
First Claim
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1. A method of producing a thin film transistor substrate, the method comprising:
- forming a gate wiring line comprising a gate electrode on an insulating substrate;
forming a data wiring line comprising a source electrode and a drain electrode on the gate wiring line;
forming a passivation layer pattern on the data wiring line except for a part of the drain electrode and a pixel region; and
forming a pixel electrode electrically connected to the drain electrode and comprising aluminum-doped zinc oxide (ZAO),wherein the forming of the passivation layer pattern comprises;
forming a passivation layer on the gate wiring line and the data wiring line;
forming a photoresist pattern on the passivation layer to remove the passivation layer from the drain electrode and the pixel region, the photoresist pattern including a first region and a second region, the first region formed on the gate wiring line and the data wiring line with the exception of a part of the drain electrode, and the second region formed between an end of the drain electrode and the pixel region, the second region being thinner than the first region; and
overetching the passivation layer using the photoresist pattern as an etching mask.
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Abstract
A thin film transistor substrate that has reduced production cost and defect rate is presented. The thin film transistor substrate includes a gate wiring line formed on an insulating substrate and including a gate electrode, a data wiring line formed on the gate wiring line and including a source electrode and a drain electrode, a passivation layer pattern formed on parts of the data wiring line other than the drain electrode and a pixel region, and a pixel electrode electrically connected to the drain electrode. The pixel electrode includes zinc oxide.
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Citations
13 Claims
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1. A method of producing a thin film transistor substrate, the method comprising:
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forming a gate wiring line comprising a gate electrode on an insulating substrate; forming a data wiring line comprising a source electrode and a drain electrode on the gate wiring line; forming a passivation layer pattern on the data wiring line except for a part of the drain electrode and a pixel region; and forming a pixel electrode electrically connected to the drain electrode and comprising aluminum-doped zinc oxide (ZAO), wherein the forming of the passivation layer pattern comprises; forming a passivation layer on the gate wiring line and the data wiring line; forming a photoresist pattern on the passivation layer to remove the passivation layer from the drain electrode and the pixel region, the photoresist pattern including a first region and a second region, the first region formed on the gate wiring line and the data wiring line with the exception of a part of the drain electrode, and the second region formed between an end of the drain electrode and the pixel region, the second region being thinner than the first region; and overetching the passivation layer using the photoresist pattern as an etching mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification