Three terminal nonvolatile memory device with vertical gated diode

• US 7,825,455 B2
• Filed: 01/23/2009
• Issued: 11/02/2010
• Est. Priority Date: 08/14/2000
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Kouznetsov, Igor G., Farmwald, Paul M., Cleeves, James M., Subramanian, Vivek, Lee, Thomas H., Johnson, Mark G.
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US12/320,351
• Publication Number:
  US 20090173985A1
• Time in Patent Office: 648 Days
• Field of Search: 257/315, 257/324
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. A three terminal nonvolatile memory cell, comprising:

a diode;

a control gate; and

a charge storage medium located between the diode and the control gate;

wherein the diode comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type;

wherein the diode comprises a vertical diode, and the second semiconductor region is located above the first semiconductor region;

wherein a first electrode which contacts the first semiconductor region is located below the first semiconductor region, and a second electrode which contacts the second semiconductor region is located above the second semiconductor region.

2. The cell of claim 1, wherein the first semiconductor region has a first conductivity type dopant density between 1×

10¹⁹ and 1×

10²¹ cm<sup>−

3</sup>, and the second semiconductor region has a second conductivity type dopant density between 1×

10¹⁹ and 1×

10²¹ cm<sup>−

3</sup>.

3. The cell of claim 2, further comprising a third semiconductor region of the first conductivity type located between the first and the second semiconductor regions.

4. The cell of claim 3, wherein the third semiconductor region has a first conductivity type dopant density between 1×

10¹⁶ and 1×

10¹⁸ cm<sup>−

3</sup>.

5. The cell of claim 1, wherein the charge storage medium contacts the second semiconductor region and the control gate contacts the charge storage medium.

6. The cell of claim 5, wherein the control gate is located above the first electrode and below the second electrode.

7. The cell of claim 5, wherein the charge storage medium comprises a dielectric isolated floating gate.

8. The cell of claim 5, wherein the charge storage medium comprises a dielectric stack.

9. The cell of claim 8, wherein the dielectric stack comprises a nitride layer located between two oxide layers.

10. The cell of claim 1, further comprising a second nonvolatile memory cell comprising a second diode and a second charge storage medium.

11. The cell of claim 10, wherein the control gate is shared between the nonvolatile memory cell and the second nonvolatile memory cell.

12. The cell of claim 11, wherein the control gate contacts the charge storage medium and the second charge storage medium.

13. The cell of claim 1, wherein the cell comprises a portion of a monolithic three dimensional array of nonvolatile memory cells.

14. The cell of claim 13, wherein cell size per bit is about (2f²)/N, where f is a minimum feature size and N is a number of device layers in a third dimension, and where N≧

1.

15. An array of nonvolatile memory cells, comprising:

a first nonvolatile memory cell comprising a first vertical diode located over a substrate and a first charge storage medium located adjacent to a side of the first vertical diode;

a second nonvolatile memory cell comprising a second vertical diode located over the substrate and a second charge storage medium located adjacent to a side of the second vertical diode;

a control gate which is located between and contacts the first charge storage medium and the second charge storage medium;

wherein;

the first nonvolatile memory cell is located adjacent to the second nonvolatile memory cell; and

the control gate is shared between the first and the second nonvolatile memory cells.

16. The array of claim 15, wherein:

the first vertical diode comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located above the first semiconductor region;

the second vertical diode comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located above the first semiconductor region; and

the first and the second charge storage medium each comprise a dielectric isolated floating gate or a dielectric stack.

17. The array of claim 16, further comprising:

a first electrode which contacts the first semiconductor region of the first vertical diode and which is located below the first semiconductor region of the first vertical diode; and

a second electrode which contacts the second semiconductor region of the first vertical diode and which is located above the second semiconductor region of the first vertical diode;

a third electrode which contacts the first semiconductor region of the second vertical diode and which is located below the first semiconductor region of the second vertical diode; and

a fourth electrode which contacts the second semiconductor region of the second vertical diode and which is located above the second semiconductor region of the second vertical diode.

18. A three terminal nonvolatile memory cell, comprising:

a first electrode;

a second electrode;

a semiconductor pillar located between the first and second electrodes, such that the semiconductor pillar is in contact with the first and the second electrodes;

a control gate; and

a charge storage medium located between the semiconductor pillar and the control gate, wherein the charge storage medium comprises;

a tunneling dielectric in contact with the semiconductor pillar;

a floating gate in contact with the tunneling dielectric; and

a control gate dielectric in contact with the floating gate;

wherein the pillar consists essentially of a diode, and the diode consists essentially of;

a first semiconductor region of a first conductivity type in contact with the first electrode and a second semiconductor of a second conductivity type in contact with the second electrode;

or

a first semiconductor region of a first conductivity type in contact with the first electrode, a second semiconductor of a second conductivity type in contact with the second electrode, and a third semiconductor region of the first conductivity type located between the first semiconductor region and the second semiconductor region.