Semiconductor device and manufacturing method therefor

• US 7,825,457 B2
• Filed: 04/27/2006
• Issued: 11/02/2010
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Okanishi, Masatomi
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): Li; Meiya
• Application Number:
  US11/414,646
• Publication Number:
  US 20070052017A1
• Time in Patent Office: 1,650 Days
• Field of Search: 257/335, 257/336, 257/344, 257/351, 257/380, 257/903, 257/E21.703, 257/E27.098, 257/E27.099, 257/E27.112, 257324-326, 257390-393, 438369-373
• US Class Current: 257/324
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a high concentration diffusion region formed in the semiconductor substrate and comprising first impurities implanted in the semiconductor substrate to a first depth from an upper face of the semiconductor substrate, the high concentration diffusion region having a first width measured orthogonal to the first depth thereof;

a first low concentration diffusion region formed only under the high concentration diffusion region and comprising the first impurities implanted at a lower concentration than the high concentration diffusion region, the first low concentration diffusion region comprising the lower concentration of the first impurities implanted in the semiconductor substrate to a second depth from the upper face of the semiconductor substrate, the first low concentration diffusion region having a second width measured orthogonal to the second depth thereof;

a first bit line formed in the semiconductor substrate and including a source region and a drain region, the first bit line including the high concentration diffusion region and the first low concentration diffusion region; and

second low concentration diffusion regions formed on each side of the high concentration diffusion region, the second low concentration diffusion regions each implanted to a third depth from the upper face of the semiconductor substrate, wherein the third depth is less than the first depth.

2. The semiconductor device as claimed in claim 1, further comprising pocket ion implantation regions formed at both sides of the high concentration diffusion region and comprising second impurities different from the first impurities of the high concentration diffusion region and the first low concentration diffusion region, the pocket ion implantation regions included in the first bit line.

3. The semiconductor device as claimed in claim 1, wherein the second width of the first low concentration diffusion region is less than the first width of the high concentration diffusion region.

4. The semiconductor device as claimed in claim 1, wherein the second width of the first low concentration diffusion region is substantially equal to the first width of the high concentration diffusion region.

5. The semiconductor device as claimed in claim 1, the second low concentration diffusion regions further comprising third impurities implanted in the semiconductor substrate at a lower concentration of impurities than the first impurities of the high concentration diffusion region, wherein the third impurities are different from the first impurities of the high concentration diffusion region and the first low concentration diffusion region, wherein the second low concentration diffusion regions are included in the bit line and wherein the third depth of the second low concentration diffusion regions is substantially less than the first depth of the high concentration diffusion region such that the second low concentration regions do not physically touch the first low concentration region.

6. The semiconductor device as claimed in claim 1, further comprising:

an ONO film provided on the semiconductor substrate; and

a word line provided on the ONO film and including a gate electrode.

7. The semiconductor device as claimed in claim 6, wherein the ONO film has multiple charge storage regions under the gate electrode and between bit lines, wherein the bit lines are identical to the first bit line.

8. The semiconductor device as claimed in claim 1, wherein the first impurities of the high concentration diffusion region and the first low concentration diffusion region are formed of arsenic ions implanted in the semiconductor substrate.

9. The semiconductor device as claimed in claim 2 wherein the second impurities of the pocket implantation regions are formed of boron ions implanted in the semiconductor substrate.

10. The semiconductor device as claimed in 5 wherein the third impurities of the second low concentration diffusion regions are formed of phosphorous ions implanted in the semiconductor substrate.

11. A semiconductor device comprising:

a semiconductor substrate;

a first diffusion region formed in the semiconductor substrate comprising first impurities implanted into the semiconductor substrate to a first depth;

a second diffusion region formed only under the first diffusion region comprising the first impurities implanted at a lower concentration than the first diffusion region into the semiconductor substrate to a second depth, the first and second diffusion regions having substantially the same width;

a first bit line formed in the semiconductor substrate and including a source region and a drain region, the first bit line including the first and second diffusion regions; and

third diffusion regions formed on each side of the first diffusion region, the third diffusion regions each implanted with second impurities into the semiconductor substrate to a third depth, wherein the second impurities are different from the first impurities, wherein the third diffusion regions are included in the bit line, and wherein the third depth is less than the first depth such that the third diffusion regions do not physically touch the second diffusion region.

12. The semiconductor device as claimed in claim 11, further comprising pocket ion implantation regions formed at both sides of the first diffusion region and comprising third impurities different from the first impurities, the pocket ion implantation regions included in the first bit line.

13. The semiconductor device as claimed in claim 11, further comprising:

an ONO film provided on the semiconductor substrate; and

a word line provided on the ONO film and including a gate electrode.

14. The semiconductor device as claimed in claim 13, wherein the ONO film has multiple charge storage regions under the gate electrode and between bit lines, wherein the bit lines are identical to the first bit line.

15. The semiconductor device as claimed in claim 11, wherein the first impurities are formed of arsenic ions implanted in the semiconductor substrate.

16. The semiconductor device as claimed in claim 12 wherein the third impurities are formed of boron ions implanted in the semiconductor substrate.

17. The semiconductor device as claimed in 11 wherein the second impurities are formed of phosphorous ions implanted in the semiconductor substrate.