Vertical field effect transistor arrays and methods for fabrication thereof

• US 7,825,460 B2
• Filed: 09/06/2006
• Issued: 11/02/2010
• Est. Priority Date: 09/06/2006
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Breitwisch, Matthew J., Lam, Chung H., Schrott, Alejandro G.
• Primary Examiner(s): Fahmy; Wael M
• Assistant Examiner(s): Kalam; Abul
• Application Number:
  US11/516,208
• Publication Number:
  US 20080054350A1
• Time in Patent Office: 1,518 Days
• Field of Search: 257229-334
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.

Claims

1. A vertical field effect transistor array semiconductor structure comprising:

a plurality of semiconductor pillars, where all vertical portions of each semiconductor pillar have a semiconductor pillar linewidth greater than a separation distance from an adjacent semiconductor pillar, and wherein at least one semiconductor pillar has a first linewidth and at least one other semiconductor pillar has a second linewidth different than the first linewidth, wherein said first linewidth of said at least one semiconductor pillar is equal to F+2s, where F is a minimum photolithographic resolvable dimension of a lithographic tool and s equals an annular linewidth of a spacer used to form at least one of said semiconductor pillars, and said second linewidth of said at least one other semiconductor pillar is equal to F+2s1+2s2, where F is as defined above, s1=s, and s2 equals a linewidth of a second spacer used in forming the at least one other semiconductor pillar;

source/drain regions located within a top portion of each semiconductor pillar and within base portions of each semiconductor pillar, wherein each neighboring semiconductor pillar shares a common source/drain region at footprints thereof;

a gate dielectric located on sidewalls and atop each semiconductor pillar, wherein a portion of said gate dielectric extends atop each common source/drain region; and

a gate electrode annularly surrounding each of said semiconductor pillars, said gate electrode is absent from atop each semiconductor pillar and said gate electrode has a thickness ¼

F, wherein F is as defined above.

2. The semiconductor structure of claim 1 wherein each semiconductor pillar has a pitch distance to an adjacent semiconductor pillar that equals twice a minimum photolithographically resolvable linewidth of a particular photolithographic apparatus.

3. The semiconductor structure of claim 1 wherein each semiconductor pillar has a substantially straight sidewall.

4. The semiconductor structure of claim 1 wherein each semiconductor pillar has a perpendicular sidewall.

5. The semiconductor structure of claim 1 wherein the plurality of semiconductor pillars comprises a plurality of channel regions within the vertical field effect transistor array.