Transistors

• US 7,825,462 B2
• Filed: 02/15/2008
• Issued: 11/02/2010
• Est. Priority Date: 09/01/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Allen, Tuman Earl III, Brown, Kris K., Tang, Sanh D., Haller, Gordon
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US12/070,078
• Publication Number:
  US 20080142882A1
• Time in Patent Office: 991 Days
• Field of Search: 257/330, 257/296, 257/401, 257/E29.26, 257/E29.262, 438/259, 438/270, 438/271, 438/589
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Claims

1. A transistor comprising:

a gate, a gate dielectric, a pair of source/drain regions, and a channel region;

the gate comprising a longitudinally oriented conductive line comprising opposing longitudinally elongated sides;

the channel region comprising a solid semiconductive material post which extends upwardly into the conductive line, and transversely relative to the longitudinal orientation of the conductive line, between the opposing longitudinally elongated sides;

the gate dielectric encircling the solid semiconductive material post; and

a portion of the channel region defining a lowermost structure of the transistor.

2. The transistor of claim 1 wherein at least portions of each of the gate, the gate dielectric, the pair of source/drain regions, and the channel region are within bulk semiconductive material of a semiconductor substrate.

3. The transistor of claim 1 wherein the channel region comprises at least three laterally spaced and parallel extending portions, one of the laterally spaced portions comprising the post.

4. The transistor of claim 3 wherein two other of the laterally spaced portions are received on opposing lateral sides of said one of the laterally spaced portions.

5. The transistor of claim 1 wherein one of the pair of source/drain regions comprises an upper portion of the post.

6. The transistor of claim 1 wherein the gate dielectric encircles one of the source/drain regions.

7. The transistor of claim 1 wherein one of the pair of source/drain regions comprises an upper portion of the post, and the gate dielectric encircles said one source/drain region.

8. The transistor of claim 1 wherein the pair of source/drain regions comprise diffusion regions within bulk monocrystalline material, said diffusion regions of the pair having elevationally outermost surfaces which are elevationally coincident with outermost surfaces of the bulk monocrystalline material.

9. A transistor comprising:

a gate, a gate dielectric, a pair of source/drain regions, and a channel region;

the channel region comprising a solid vertically extending semiconductive material post;

one of the pair of source/drain regions comprising an upper portion of the solid vertically extending semiconductive material post;

the gate dielectric encircling the solid semiconductive material post; and

a portion of the channel region defining a lowermost structure of the transistor.

10. The transistor of claim 9 wherein the semiconductive material comprises silicon.

11. The transistor of claim 10 wherein the semiconductive material comprises monocrystalline silicon of a bulk monocrystalline silicon substrate.

12. The transistor of claim 9 wherein the pair of source/drain regions comprise diffusion regions within bulk monocrystalline material, said diffusion regions of the pair having elevationally outermost surfaces which are elevationally coincident with outermost surfaces of the bulk monocrystalline material.

13. The transistor of claim 9 wherein at least portions of each of the gate, the gate dielectric, the pair of source/drain regions, and the channel region are within bulk semiconductive material of a semiconductor substrate.

14. The transistor of claim 9 wherein one of the pair of source/drain regions comprises an upper portion of the post.