Device and method for balancing charge between the individual cells of a double-layer capacitor

• US 7,825,638 B2
• Filed: 09/01/2006
• Issued: 11/02/2010
• Est. Priority Date: 09/02/2005
• Status: Expired due to Fees

• Current Assignee: Vitesco Technologies GmbH (Continental AG)
• Original Assignee: VDO Automotive AG (Continental AG)
• Inventors: Bolz, Stephan, Knorr, Rainer, Götzenberger, Martin
• Primary Examiner(s): Tso; Edward
• Assistant Examiner(s): OMAR, AHMED H
• Application Number:
  US12/065,543
• Publication Number:
  US 20080252266A1
• Time in Patent Office: 1,523 Days
• Field of Search: 320/166, 320/167
• US Class Current: 320/166
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries

Abstract

A device and a method for balancing charge between individual cells of a double-layer capacitor, in particular in a multi-voltage motor vehicle electrical system. Each individual cell of the double-layer capacitor is associated with a capacitor, the first terminal of which can be connected via a first switch to a first terminal of the associated cell and via a second switch to a second terminal of the associated cell, and the second terminal of which is connected to the second terminals of all of the capacitors.

Claims

1. A device for charge balancing between individual cells having first and second terminals in a double-layer capacitor, especially in a multi-voltage motor vehicle electrical system, the device comprising:

capacitors each being assigned to a respective one of the individual cells of the double-layer capacitor, said capacitors each having first and second terminals;

first switches each for connecting said first terminal of one of said capacitors to the first terminal of the respective assigned cell;

second switches each for connecting said first terminal of one of said capacitors to the second terminal of the respective assigned cell; and

said second terminals of all of said capacitors being interconnected;

wherein

said first and second switches are MOS-FET switching transistors having source and drain terminals in a charge balancing circuit for single operation;

said first terminals of said capacitors are each connected to said source terminal of a respective one of said first switching transistors and to said drain terminal of a respective one of said second switching transistors;

a node is connected at said interconnected said second terminals of said capacitors;

said drain terminals of said first switching transistors are each connected to said first terminal of the respective assigned cell;

said source terminals of said second switching transistors are each connected to said second terminal of the respective assigned cell; and

series circuits of two resistors are each connected in parallel to a respective one of the cells and each have a connection point connected to said first terminal of said respective assigned capacitor.

2. The device according to claim 1, wherein:

said first and second switches are MOS-FET switching transistors having source and drain terminals in another charge balancing circuit for differential operation connected in parallel with said charge balancing circuit for single operation;

said first terminals of said capacitors are each connected to said source terminal of a respective one of said first switching transistors and to said drain terminal of a respective one of said second switching transistors;

another node is connected at said interconnected second terminals of said capacitors;

said drain terminals of said first switching transistors are each connected to the first terminal of the respective assigned cell;

said source terminals of said second switching transistors are each connected to the second terminal of the respective assigned cell; and

series circuits of two resistors are each connected in parallel to a respective one of the cells and each have a connection point connected to said first terminal of said respective assigned capacitor.

3. The device according to claim 1, which further comprises an activation circuit for each of said switching transistors, including:

a series circuit of a logic buffer and a coupling capacitor for conveying an activation signal to a gate terminal of a respective one of said switching transistors;

a Zener diode connected between said source and gate terminals of said respective one of said switching transistors and having a cathode connected to said gate terminal; and

a resistor connected in parallel to said Zener diode.

4. The device according to claim 1, which further comprises:

a recharging circuit including;

a switch connected to an external source of energy;

a switchable current source receiving constant current through said switch from the external source of energy; and

a recharging capacitor having one terminal connected to reference potential and another terminal connected to said switchable current source at a connection point for charging; and

for single operation;

a voltage divider connected in parallel to said charging capacitor and having two resistors of equal size with a connection point therebetween;

a switching transistor having a drain terminal connected to said connection point of said current source and said recharging capacitor and a source terminal connected to said node and to said connection point of said two resistors; and

another switching transistor having a drain terminal connected to said node and a source terminal connected to reference potential.

5. The device according to claim 1, which further comprises, for differential operation:

another recharging circuit connected in parallel to said recharging circuit and including a voltage divider connected in parallel to said recharging capacitor and having two resistors of equal size with a connection point therebetween;

a switching transistor having a drain terminal connected to said connection point of said current source and said recharging capacitor and a source terminal connected to said node and to said connection point of said two resistors; and

another switching transistor having a drain terminal connected to said node and a source terminal connected to reference potential.

6. The device according to claim 1, which further comprises a rectifier constructed as a synchronous demodulator with an input connected in single operation to said node of said charge balancing circuit.

7. The device according to claim 1, which further comprises, for differential operation:

two changeover switches, said changeover switches in one setting connecting said input of said rectifier to said node of said charge balancing circuit and connecting another input of said rectifier to said other node of said charge balancing circuit, and said changeover switches in another setting connecting said input of said rectifier to said other node of said charge balancing circuit and connecting said other input of said rectifier to said node of said charge balancing circuit; and

said two changeover switches being switched over synchronously by said activation signal AS of said switching transistor assigned to the cell having a charge voltage to be measured.

8. The device according to claim 1, which further comprises a resistor for single operation having one terminal connected to said node of said charge balancing circuit and another terminal connected to a reference voltage.

9. The device according to claim 1, which further comprises resistors for differential operation each having one terminal connected to a respective one of said nodes of said charge balancing circuit and another terminal applied to a reference voltage.

11. A method for operating the device according to claim 1, the method comprising the following steps:

alternately switching said switching transistors assigned to a cell to be conductive with a predetermined frequency for measuring a charge voltage of the cell in single mode; and

converting a square-wave ac voltage arising at said node at a high dc voltage potential in a rectifier to a dc voltage corresponding to the subsequently stored charge voltage with reference to a reference potential.

12. The method according to claim 11, which further comprises switching said switching transistors assigned to a cell to be conductive simultaneously and phase-opposed to others of said switching transistors, for measurement of the charge voltage of said cell with differential operation, causing square-wave alternating current voltages phase-opposed to each other to be produced at nodes and, with a peak-to-peak value being translated in said rectifier to a direct current voltage corresponding to a subsequently stored charge voltage with reference to reference potential.

13. The method according to claim 11, which further comprises measuring and storing the charge voltage of all of said cells at periodic intervals.

14. The method according to claim 11, which further comprises:

comparing the stored values of the charge voltages of all of said cells at periodic intervals for differences therebetween and with a predetermined maximum value; and

if one or more differences lie beyond a predetermined limit value or if one or more values lie beyond the predetermined maximum value, carrying out charge balancing consecutively between said cell being charged the most and said cell being charged the least.

15. The method according to claim 13, which further comprises forming a total of the stored values of the charge voltage and comparing the total with a predetermined minimum value, and, if the minimum value is undershot, recharging individual cells, cell groups or the entire double-layer capacitor from an external source of energy.

16. The method according to claim 14, which further comprises charge balancing from a more highly-charged cell to a less highly-charged cell in a single mode by:

switching said first switching transistor of said more highly-charged cell and said first switching transistor of said less highly-charged cell to be conductive at a predetermined frequency in a first step, causing said capacitors connected in series, assigned to said cells to be charged to a voltage V1=V_C1+V_C2+. . . +V<sub>Cn−

1</sub>; and

switching said first switching transistors to be non-conductive and switching said second switching transistor of said more highly-charged cell and said second switching transistor of said less highly-charged cell to be conductive in a second step, with said cells having a lower voltage V2 =VC2+. . . +VCn−

1+VCn than the voltage V1 at the capacitors;

causing a balancing current to flow from said capacitors assigned to said cells to be recharged into said less highly-charged cell; and

repeating said first and second steps until both cells exhibit approximately the same charge voltage.

17. The method according to claim 16, which further comprises, for differential operation:

simultaneously switching said first switching transistors and said second switching transistors to be conductive in said first step; and

simultaneously switching said second switching transistors and said first switching transistors to be conductive in said second step.

18. The method according to claim 16, which further comprises, for a fast charge balance in the double-layer capacitor:

simultaneously switching all of said first switching transistors of one side and all of said second switching transistors of another side to be conductive in said first step; and

simultaneously switching all of said second switching transistors of one side and all of said first switching transistors of another side to be conductive in said second step.

19. The method according to claim 15, which further comprises:

charging said recharging capacitor through said switchable current source and a switch from an external source of energy with constant current to a predetermined voltage for recharging a cell; and

subsequently transmitting charge from said recharging capacitor to said cell to be charged by;

simultaneously switching said switching transistor and said first switching transistor assigned to said cell, to be charged to be conductive in single operation; and

simultaneously switching said switching transistor, said first switching transistor assigned to said cell to be charged, said switching transistor and said second switching transistor assigned to said cell to be charged, to be conductive in differential operation.

20. The method according to claim 11, which further comprises executing all of said steps under program control with microprocessors.

10. A multi-voltage motor vehicle electrical system, comprising:

a double-layer capacitor including individual cells having first and second terminals; and

a device for charge balancing between said individual cells, said device including;

capacitors each being assigned to a respective one of said individual cells of said double-layer capacitor, said capacitors each having first and second terminals;

first switches each for connecting said first terminal of one of said capacitors to said first terminal of said respective assigned cell;

second switches each for connecting said first terminal of one of said capacitors to said second terminal of said respective assigned cell; and

said second terminals of all of said capacitors being interconnected;

wherein

said first and second switches are MOS-FET switching transistors having source and drain terminals in a charge balancing circuit for single operation;

said first terminals of said capacitors are each connected to said source terminal of a respective one of said first switching transistors and to said drain terminal of a respective one of said second switching transistors;

a node is connected at said interconnected said second terminals of said capacitors;

said drain terminals of said first switching transistors are each connected to said first terminal of the respective assigned cell;

said source terminals of said second switching transistors are each connected to said second terminal of the respective assigned cell; and

series circuits of two resistors are each connected in parallel to a respective one of the cells and each have a connection point connected to said first terminal of said respective assigned capacitor.