Integrated circuit comparator or amplifier

• US 7,825,700 B2
• Filed: 01/22/2009
• Issued: 11/02/2010
• Est. Priority Date: 08/30/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US12/357,549
• Publication Number:
  US 20090128195A1
• Time in Patent Office: 649 Days
• Field of Search: 327 65- 67, 327/563
• US Class Current: 327/65
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45664 the LC comprising one or more cascaded inverter stages as output stage at one output of the dif amp circuit
• CPC Class Codes: H03F 2203/45666 the LC comprising two anti-phase controlled inverter circuits as output stages, e.g. fully differential
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Claims

1. A differential amplifier comprising:

a first transistor having a first gate terminal and a first source or drain terminal;

a second transistor having a second gate terminal coupled to the first gate terminal and a second source or drain terminal;

a source follower circuit having an input terminal coupled to the first source or drain terminal and an output terminal coupled to the first and second gate terminals;

a third transistor having a third gate terminal configured to receive a reference signal and a third source or drain terminal coupled to the first source or drain terminal; and

a fourth transistor having a fourth gate terminal configured to receive an input signal and a fourth source or drain terminal coupled to the second source or drain terminal.

2. The differential amplifier of claim 1 wherein

the source follower circuit comprises a fifth transistor, the input terminal comprises a fifth gate terminal of the fifth transistor, and the output terminal comprises a fifth source or drain terminal of the fifth transistor.

3. The differential amplifier of claim 2 wherein the source follower circuit comprises a sixth transistor having a sixth source or drain terminal coupled to the fifth source or drain terminal.

4. The differential amplifier of claim 1 wherein the differential amplifier is configured to provide an output signal at the fourth source or drain terminal, the output signal based in part on the input signal and the reference signal.

5. The differential amplifier of claim 1 wherein the first transistor has a fifth source or drain terminal coupled to a power supply and wherein a voltage between the power supply and the first gate terminal is based in part on the source follower circuit.

6. An inverter amplifier comprising:

a first output terminal;

an input terminal;

a first transistor having a first gate coupled to the input terminal, a second terminal coupled to the first output terminal, and a third terminal coupled to a first power supply voltage;

a source follower circuit coupled to the input terminal, the source follower circuit having a second output terminal; and

a second transistor having a second gate coupled to the second output terminal, a fourth terminal coupled to a second power supply voltage, and a fifth terminal coupled to the first output terminal, the second transistor configured to couple the second power supply voltage to the first output terminal when conductive.

7. The inverter amplifier of claim 6 wherein the source follower circuit comprises a third transistor having a third gate coupled to the input terminal, a sixth terminal coupled to the second power supply voltage, and a seventh terminal coupled to the second output terminal.

8. The inverter amplifier of claim 6 wherein a voltage between the second power supply voltage and the second gate of the second transistor is based in part on the source follower circuit.

9. A comparator comprising:

a differential amplifier comprising;

a first transistor having a first gate terminal and a first source or drain terminal;

a second transistor having a second gate terminal coupled to the first gate terminal and a second source or drain terminal;

a first source follower circuit having a first input terminal coupled to the second source or drain terminal and a first output terminal coupled to the first and second gate terminals;

a third transistor having a third gate terminal configured to receive a reference signal and a third source or drain terminal coupled to the first source or drain terminal; and

a fourth transistor having a fourth gate terminal configured to receive an input signal and a fourth source or drain terminal coupled to the second source or drain terminal; and

an inverter amplifier coupled to the differential amplifier, the inverter amplifier comprising;

a second source follower circuit having a second input terminal coupled to the fourth source or drain terminal, and a second output terminal;

a fifth transistor having a fifth gate terminal coupled to the second output terminal and a fifth source or drain terminal configure to generate an inverted output signal based in part on a signal at the second input terminal.

10. A method for comparing an input signal and a reference signal, the method comprising:

receiving the input signal and the reference signal at input terminals of a differential amplifier having at least two transistors;

applying a first gate voltage to the at least two transistors in part using a first source follower circuit;

generating a first output signal at a terminal of at least one of the two transistors; and

receiving the first output signal at an inverter amplifier including at least a third transistor;

applying a second gate voltage to the third transistor in part using a second source follower circuit; and

generating a second output signal at a terminal of the third transistor based in part on the first output signal.

11. The method of claim 10 wherein the differential amplifier is coupled between a first and second power supply voltage, a voltage difference between the first gate voltage and the first or second power supply voltage being greater than half a difference between the first and second power supply voltages.

12. The method of claim 11 wherein the inverter amplifier is coupled between the first and second power supply voltages and a voltage difference between the second gate voltage and the first or second power supply voltage is greater than half the difference between the first and second power supply voltages.

13. The method of claim 10 further comprising biasing the first and second source follower circuits with a bias voltage.

14. The method of claim 13 further comprising biasing the differential amplifier in part based on the bias voltage.