Method for controlling a universal backlight inverter

• US 7,825,883 B2
• Filed: 04/13/2007
• Issued: 11/02/2010
• Est. Priority Date: 04/14/2006
• Status: Expired due to Fees

• Current Assignee: Monolithic Power Systems Incorporated
• Original Assignee: Monolithic Power Systems Incorporated
• Inventors: Yao, Kaiwei
• Primary Examiner(s): Dharia; Prabodh M
• Application Number:
  US11/735,370
• Publication Number:
  US 20070242022A1
• Time in Patent Office: 1,299 Days
• Field of Search: 345/87, 345/99, 345/102, 345/204, 345/211, 345/212, 345/905, 315/169.3, 315/224, 315/302, 368/67, 348/221.1, 178/18.04
• US Class Current: 345/87
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

The present invention introduces methods to modify the burst frequency of an inverter in a given LCD panel without any component change on the inverter board. The present invention also introduces methods to adjust the setting of a sensing system for duty cycles and accept Display Power Saving Technology (DPST) input signals with different frequencies. The universal inverter module with the present invention can be applied for different DPST technologies.

Claims

1. A method for deriving a burst output signal in a LCD panel, wherein said LCD panel contains an inverter and a computer system, wherein said inverter has a duty cycle D and contains a bus controller and a counter, comprising:

sending a predetermined burst frequency from said computer system to said bus controller through a bus;

deriving the frequency of said counter through said bus controller, wherein the frequency of said counter is at least the required resolution steps, N, times the required burst frequency, wherein said counter has M bits and 2^M≧

N;

deriving the high level portion of said burst output signal through said inverter by counting D*N through said counter, wherein said counter starts to count after the high level portion is detected and triggers the low level of said burst output signal after D*N counts; and

deriving the low level portion of said burst output signal through said inverter by counting (1−

D)*N through said counter, wherein said counter starts to count after the low level portion is detected and triggers the high level of said burst output signal after (1−

D)*N counts.

2. The method of claim 1, wherein said burst output signal can be either stored in said bus controller permanently, or programmed repeatedly.

3. The method of claim 1, wherein said bus is either a System Management Bus (SMBus) or an Inter-IC-bus (IIC bus).

4. The method of claim 1, wherein said predetermined burst frequency is either a real value or a value from a lookup table.

5. A method for sensing the duty cycle of a Display Power Saving Technology (DPST) input signal in a LCD panel, wherein said LCD panel contains a graphic card, an inverter, and a computer system, wherein said inverter contains a bus controller and a counter, comprising:

sending said DPST input signal from said graphic card to said bus controller;

deriving the frequency of said counter through said bus controller, wherein the frequency of said counter is at least the required resolution steps, N, times the frequency of said DPST input signal, wherein said counter has M bits and 2^M≧

N;

deriving a high level count, H, through said counter when said DPST input signal is high, wherein said counter starts to count said high level count when the high level of said DPST input signal is detected and stops counting said high level count when the low level of said DPST input signal is detected;

deriving a low level count, L, through said counter when said DPST input signal is low, wherein said counter starts to count said low level count when the low level of said DPST input signal is detected and stops counting said low level count when the high level of said DPST input signal is detected; and

deriving said duty cycle of said DPST input signal by dividing H over (H+L) through said bus controller.

6. The method of claim 5, wherein said bus is either a System Management Bus (SMBus) or an Inter-IC-bus (IIC bus).

7. The method for digitally transferring a Display Power Saving Technology (DPST) signal in a LCD panel, wherein said LCD panel contains a graphic card, an inverter, and a computer system, wherein said inverter contains a bus controller and a counter, comprising:

obtaining a DPST signal digitally from said graphic card through said computer system through a bus; and

sending said DPST signal from said computer system to said bus controller through said bus.