Low cost high density rectifier matrix memory

• US 7,826,244 B2
• Filed: 07/20/2007
• Issued: 11/02/2010
• Est. Priority Date: 06/22/2000
• Status: Expired due to Fees

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R.
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): Le, Toan
• Application Number:
  US11/780,909
• Publication Number:
  US 20080016414A1
• Time in Patent Office: 1,201 Days
• Field of Search: 365/163, 365/51, 365/113, 365/115, 365/230.06, 438/95
• US Class Current: 365/51
• CPC Class Codes: G06K 5/04 Verifying the alignment of markings
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Claims

1. An electronic memory device comprising:

a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations; and

error detection and correction logic interconnected to at least one of the layers of memory circuitry,

wherein the error detection and correction logic is disposed on a substrate disposed beneath the plurality of layers of memory circuitry.

2. The electronic memory device of claim 1, wherein the substrate comprises a semiconductor material.

3. The electronic memory device of claim 1, further comprising a microprocessor disposed on the substrate, the microprocessor comprising the error detection and correction logic.

4. An electronic memory device comprising:

a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations; and

data decryption logic interconnected to at least one of the layers of memory circuitry,

wherein the data decryption logic is disposed on a substrate disposed beneath the plurality of layers of memory circuitry.

5. The electronic memory device of claim 4, wherein the substrate comprises a semiconductor material.

6. The electronic memory device of claim 4, further comprising a microprocessor disposed on the substrate, the microprocessor comprising the data decryption logic.

7. The electronic memory device of claim 4, wherein the data decryption logic comprises data encryption circuitry.

8. The electronic memory device of claim 4, wherein the data decryption logic utilizes a DES algorithm.

9. The electronic memory device of claim 4, wherein the data decryption logic utilizes a PGP algorithm.

10. An electronic memory device comprising:

a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations; and

data encryption logic interconnected to at least one of the layers of memory circuitry,

wherein the layer of data encryption logic is disposed on a substrate disposed beneath the plurality of layers of memory circuitry.

11. The electronic memory device of claim 10, wherein the substrate comprises a semiconductor material.

12. The electronic memory device of claim 10, further comprising a microprocessor disposed on the substrate, the microprocessor comprising the data encryption logic.

13. The electronic memory device of claim 10, wherein the data encryption logic utilizes a DES algorithm.

14. The electronic memory device of claim 10, wherein the data encryption logic utilizes a PGP algorithm.

15. An electronic memory device comprising:

a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations; and

data compression logic interconnected to at least one of the layers of memory circuitry,

wherein the data compression logic is disposed on a substrate disposed beneath the plurality of layers of memory circuitry.

16. The electronic memory device of claim 15, wherein the substrate comprises a semiconductor material.

17. The electronic memory device of claim 15, further comprising a microprocessor disposed on the substrate, the microprocessor comprising the data compression logic.

18. The electronic memory device of claim 15, wherein the data compression logic utilizes an MP3 algorithm.

19. An electronic memory device comprising:

a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations; and

data decompression logic interconnected to at least one of the layers of memory circuitry,

wherein the data decompression logic is disposed on a substrate disposed beneath the plurality of layers of memory circuitry.

20. The electronic memory device of claim 19, wherein the substrate comprises a semiconductor material.

21. The electronic memory device of claim 19, further comprising a microprocessor disposed on the substrate, the microprocessor comprising the data decompression logic.

22. The electronic memory device of claim 19, wherein the data decompression logic utilizes an MP3 algorithm.