Memory with output control
First Claim
1. A device into which a clock input (CLKI) signal is received, and out of which a clock output (CLKO) signal is transmitted, the device comprising:
- flash memory;
input connections for receiving data, an output enable signal, and the CLKI signal that provides for synchronization with respect to the received data;
output connections for transmitting the CLKO signal, and for transmitting the data in response to the output enable signal being held to a logic level for a number of edges of the CLKO signal that provides for other synchronization; and
a Phase Lock Loop (PLL) to match any phase difference between the CLKI and CLKO signals.
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0 Petitions
Accused Products
Abstract
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
151 Citations
29 Claims
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1. A device into which a clock input (CLKI) signal is received, and out of which a clock output (CLKO) signal is transmitted, the device comprising:
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flash memory; input connections for receiving data, an output enable signal, and the CLKI signal that provides for synchronization with respect to the received data; output connections for transmitting the CLKO signal, and for transmitting the data in response to the output enable signal being held to a logic level for a number of edges of the CLKO signal that provides for other synchronization; and a Phase Lock Loop (PLL) to match any phase difference between the CLKI and CLKO signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A device into which a clock input (CLKI) signal is received, and out of which a clock output (CLKO) signal is transmitted, the device comprising:
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flash memory; input connections for receiving data, an output enable signal, and the CLKI signal that provides for synchronization with respect to the received data; output connections for transmitting the CLKO signal, and for transmitting the data in response to an output enable signal being held to a logic level for a number of edges of the CLKO signal that provides for other synchronization; and a DLL to match any phase difference between the CLKI and CLKO signals. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A flash memory system having a plurality of serially connected flash memory devices comprising:
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a first flash memory device having a plurality of data input ports for receiving data from an external source, a plurality of data output ports for providing data received at the data input ports, a plurality of control input ports for receiving at least an output enable signal from the external source, and a plurality of control output ports for providing at least the output enable signal, and the first flash memory device being configured to provide the data in response to the output enable signal; and a second flash memory device having a plurality of data input ports for receiving the data provided from the data output ports of the first flash memory device, a plurality of data output ports for providing the data received at the data input ports, a plurality of control input ports for receiving at least the output enable signal, and a plurality of control output ports for providing at least the output enable signal, and the second flash memory device being configured to provide the data in response to the output enable signal. - View Dependent Claims (18, 19, 20, 21)
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22. A device into which a clock input (CLKI) signal is received, the device comprising:
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flash memory; at least one port for receiving a command, the CLKI signal providing synchronization with respect to the command; control signal ports for receiving two control signals, the command being latched on edges of the CLKI signal while only one of the two control signals is held at a logic level for at least a duration of time the command is provided to the device; and
,core circuitry for executing an operation corresponding to the command. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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Specification