Circuits, architectures, systems, methods, algorithms and software for reducing contention and/or handling channel access in a network

• US 7,826,438 B1
• Filed: 07/19/2004
• Issued: 11/02/2010
• Est. Priority Date: 04/26/2004
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Narasimhan, Ravi, Salhotra, Atul, Kopikare, Rahul
• Primary Examiner(s): Patel; Ajit
• Assistant Examiner(s): NGUYEN, KHAI MINH
• Application Number:
  US10/895,006
• Time in Patent Office: 2,297 Days
• Field of Search: 370/345, 370/349, 370/445, 370/400, 370/448, 370/465, 370/447
• US Class Current: 370/345
• CPC Class Codes: H04L 1/188 Time-out mechanisms
• CPC Class Codes: H04L 1/1887 Scheduling and prioritising arrangements

Abstract

Methods, circuits and architectures for managing channel access and/or reducing contention in network transmissions where such transmissions may not be acknowledged within a certain time period, computer programs adapted to implement such methods, and systems and networks including such circuits/architectures. When the information is not so acknowledged, the methods generally include (1) waiting for a predetermined time period before attempting to retransmit the information, and/or (2) retransmitting the information. The action taken may depend on the priority of the information. The circuit and/or architecture generally includes (a) a transmitter, (b) a priority detector, and when the information is not acknowledged within a certain time period, (c) logic for (i) retransmitting the information having a first priority and (ii) waiting before attempting to retransmit information having a second priority. The present invention has particular advantage in wireless networks and advantageously improves network transmission efficiency, reliability and/or performance.

Claims

1. A circuit for transmitting information over a network, the circuit comprising:

a) a transmitter configured to transmit said information over a channel in said network, and retain access to said channel until either said information transmitted over said channel is acknowledged by a receiving station, or for at least a first predetermined period of time following transmission of said information, whichever is shorter;

b) a detector configured to determine a type for said information;

c) transmitter instruction logic receiving a timeout signal and comprising acknowledgement detection logic that determines whether said information transmitted over said channel is acknowledged within said first predetermined period of time, and, when said information transmitted over said channel is not acknowledged by said receiving station within said first predetermined period of time following transmission of said information, said transmitter instruction logic instructs said transmitter to;

i) retransmit said information when said information has a first type, or

ii) wait for a second predetermined period of time before attempting to retransmit said information when said information has a second type; and

d) at least one timer that generates said timeout signal when said first predetermined period of time expires, said timeout signal comprising one of (i) a first timeout signal corresponding to a first value for said first predetermined period of time when said channel is in use, and (ii) a second timeout signal corresponding to a second value for said first predetermined period of time when said channel is not in use, said first and second predetermined periods of time being different from each other.

2. The circuit of claim 1, wherein said type is a priority state.

3. The circuit of claim 2, wherein said first type corresponds to a high priority.

4. The circuit of claim 2, wherein said second type corresponds to a low priority.

5. The circuit of claim 1, wherein (i) said information comprises a plurality of information blocks, and (ii) following transmission of a first information block, said transmitter transmits a second information block when said first information block is acknowledged within said first predetermined period of time.

6. The circuit of claim 5, wherein said transmitter retains access to said channel during a transmission period, said transmission period encompassing said first information block transmission, said first predetermined period of time and said second information block transmission.

7. The circuit of claim 1, wherein said transmitter comprises a wireless transmitter.

8. The circuit of claim 7, wherein said wireless transmitter is compatible with IEEE Standard 802.11e.

9. The circuit of claim 8, wherein said type comprises an access category.

10. The circuit of claim 9, wherein said first type corresponds to a voice and/or video access category.

11. The circuit of claim 9, wherein said second type corresponds to a best effort or background access category.

12. The circuit of claim 1, wherein said circuit is compatible with one or more of IEEE Standards 802.11a, 802.11b, 802.11e, 802.11g and/or 802.11n.

13. The circuit of claim 1, wherein said transmitter instruction logic comprises at least one multiplexer configured to select one of said first and second timeout signals in response to a channel use control signal.

14. The circuit of claim 1, wherein said first value for said first predetermined period of time comprises a length of said first information block and a minimum interference spacing.

15. The circuit of claim 14, wherein said first value for said first predetermined period of time has a maximum length of said first information block length and an arbitration interference spacing.

16. The circuit of claim 1, wherein said second value for said first predetermined period of time comprises a length of said first information block, a minimum interference spacing, and an acknowledgement length.

17. The circuit of claim 1, wherein said acknowledgement detection logic comprises at least one logic gate that receives said timeout signal and an acknowledgement signal, and informs said transmitter instruction logic whether said information was acknowledged within said first predetermined period of time.

18. The circuit of claim 1, further comprising a counter configured to count a number of retransmissions of said information from said transmitter.

19. The circuit of claim 18, further comprising transmission rate lowering logic that instructs said transmitter to retransmit said information at a lower rate in response to a first count signal from said counter indicating a first predetermined number of retransmissions.

20. The circuit of claim 18, further comprising wait instruction logic that instructs said transmitter to wait for said second predetermined period of time before attempting again to retransmit said information in response to a second count signal from said counter indicating a second predetermined number of retransmissions.

21. The circuit of claim 1, wherein said type comprises a direction, a latency characteristic, or a transmission rate.

22. The circuit of claim 21, wherein said first type corresponds to a downstream direction, a low latency, or a relatively high transmission rate.

23. The circuit of claim 21, wherein said second type corresponds to an upstream direction, a latency characteristic other than a low latency, or a relatively low transmission rate.

24. The circuit of claim 11, embodied on a single integrated circuit.

25. A media access control device, comprising the circuit of claim 1.

26. A system, comprising:

a) the circuit of claim 1;

b) at least one access point communicatively coupled to said circuit; and

c) at least one station communicatively coupled to said circuit.

27. The system of claim 26, comprising a plurality of said stations, but wherein said at least one access point consists of one access point and said first type corresponds to a downstream direction.

28. The system of claim 27, wherein at least one station comprises a station and said second type corresponds to an upstream direction.

29. The system of claim 26, wherein said system comprises a wireless network.

30. The system of claim 29, wherein said system comprises an IEEE 802.11e-compliant network.

31. A circuit for reducing contention in transmissions of information, comprising:

a) means for transmitting said information over a channel in said network, and for retaining access to said channel until either said information transmitted over said channel is acknowledged by a means for receiving said information, or for at least a first predetermined period of time following transmission of said information, whichever is shorter;

b) means for detecting or determining a type for said information; and

c) when said information is not acknowledged within said first predetermined period of time, means for (i) retransmitting said information when said information has a first type and (ii) waiting for a second predetermined period of time before attempting to retransmit said information when said information has a second type, wherein said means for retransmitting and waiting receives a timeout signal and comprises acknowledgement detection logic that determines whether said information transmitted over said channel is acknowledged within said first predetermined period of time; and

d) at least one timer that generates said timeout signal when said first predetermined period of time expires, said timeout signal comprising one of (i) a first timeout signal corresponding to a first value for said first predetermined period of time when said channel is in use, and (ii) a second timeout signal corresponding to a second value for said first predetermined period of time when said channel is not in use, said first and second predetermined periods of time being different from each other.

32. The circuit of claim 31, wherein said type is a priority state.

33. The circuit of claim 32, wherein said first type corresponds to a high priority.

34. The circuit of claim 32, wherein said second type corresponds to a low priority.

35. The circuit of claim 31, wherein (i) said information comprises a plurality of information blocks, and (ii) following transmission of a first information block, said means for transmitting transmits a second information block when said first information block is acknowledged within said first predetermined period of time.

36. The circuit of claim 35, wherein said means for transmitting retains access to said channel during a transmission period, said transmission period encompassing said first information block transmission, said first predetermined period of time and said second information block transmission.

37. The circuit of claim 31, wherein said means for transmitting comprises a wireless transmitter.

38. The circuit of claim 37, wherein said wireless transmitter is compatible with IEEE Standard 802.11e.

39. The circuit of claim 38, wherein said type comprises an access category.

40. The circuit of claim 39, wherein said first type corresponds to a voice and/or video access category.

41. The circuit of claim 39, wherein said second type corresponds to a best effort or background access category.

42. The circuit of claim 31, wherein said circuit is compatible with one or more of IEEE Standards 802.11a, 802.11b, 802.11e, 802.11g and/or 802.11n.

43. The circuit of claim 31, wherein said means for retransmitting and waiting comprises at least one means for selecting one of said first and second timeout signals in response to a channel use control signal.

44. The circuit of claim 31, wherein said first value for said first predetermined period of time comprises a length of said first information block and a minimum interference spacing.

45. The circuit of claim 44, wherein said first value for said first predetermined period of time has a maximum length of said first information block length and an arbitration interference spacing.

46. The circuit of claim 31, wherein said second value for said first predetermined period of time comprises a length of said first information block, a minimum interference spacing, and an acknowledgement length.

47. The circuit of claim 31, wherein said acknowledgement detection logic comprises at least one logic gate configured to (i) receive a timeout signal and an acknowledgement signal, and (ii) inform said means for retransmitting and waiting whether said information was acknowledged within said first predetermined period of time.

48. The circuit of claim 31, further comprising a means for counting a number of retransmissions of said information from said transmitter.

49. The circuit of claim 48, further comprising a means for reducing a transmission rate of said means for transmitting, said information means for reducing being responsive to a first count signal from said means for counting.

50. The circuit of claim 48, further comprising means for instructing said means for transmitting to wait for said second predetermined period of time before attempting again to retransmit said information, said means for instructing being responsive to a second count signal from said means for counting.

51. The circuit of claim 31, wherein said type comprises a direction or a latency characteristic.

52. The circuit of claim 51, wherein said first type corresponds to a downstream direction or a low latency.

53. The circuit of claim 51, wherein said second type corresponds to an upstream direction or a latency characteristic other than a low latency.

54. The circuit of claim 31, embodied on a single integrated circuit.

55. A media access control device, comprising the circuit of claim 31.

56. A system, comprising:

a) the circuit of claim 31;

b) at least one means for externally accessing said system or network, communicatively coupled to said circuit; and

c) at least one means for transmitting and/or receiving said information, communicatively coupled to (i) said circuit and (ii) said means for externally accessing said system or network, said at least one means for transmitting and/or receiving said information being only internally accessible to said system or network.

57. The system of claim 56, comprising a plurality of said means for transmitting and/or receiving said information, but wherein said at least one means for externally accessing said system consists of one access point and said first type corresponds to a downstream direction.

58. The system of claim 57, wherein at least one means for transmitting and/or receiving said information comprises a station and said second type corresponds to an upstream direction.

59. The system of claim 56, wherein said system comprises a wireless network.

60. The system of claim 59, wherein said system comprises an IEEE 802.11e-compliant network.