Method and apparatus for providing coherent phase noise in transceivers or similar systems

• US 7,826,519 B1
• Filed: 10/28/2005
• Issued: 11/02/2010
• Est. Priority Date: 05/23/2005
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Tse, Lawrence, Tsai, King Chun
• Primary Examiner(s): Pathak; Sudhanshu C
• Application Number:
  US11/260,113
• Time in Patent Office: 1,831 Days
• Field of Search: 455/296, 455/73, 370/537, 327/147, 331/14, 710/312
• US Class Current: 375/219
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

A method and circuit for providing coherent phase noise including a clock receiver to receive a clock signal generated external to the circuit and a local clock source arranged on the circuit. The circuit further includes a selector to select an output of one of the clock receiver and the local clock source and a wireless transceiver responsive to an output of the selector.

Claims

1. An integrated circuit comprising:

a clock receiver configured to receive an external clock signal generated external to the integrated circuit;

a local clock source arranged on the integrated circuit and configured to generate a local clock signal;

a selector configured to select one of said external clock signal and said local clock signal;

a clock transmitter configured to transmit the selected one of the said external clock signal and said local clock signal externally to the integrated circuit; and

a wireless transceiver configured to determine which one of a plurality modes to operate and further configured to operate in a determined one of the plurality of modes, wherein the plurality modes comprise;

an autonomous mode in which said selector selects the local clock signal;

a master mode in which said selector selects the local clock signal and said clock transmitter transmits the selected local clock signal;

a slave mode in which said selector selects the external clock signal; and

a repeat mode in which said selector selects the external clock signal and said clock transmitter transmits the selected external clock signal,

wherein the wireless transceiver activates the local clock source and deactivates the clock receiver and the clock transmitter in the autonomous mode,

wherein the wireless transceiver activates the local clock source and the clock transmitter and deactivates the clock receiver in the master mode,

wherein the wireless transceiver activates the clock receiver and deactivates the local clock source and the clock transmitter in the slave mode, and

wherein the wireless transceiver activates the clock receiver and the clock transmitter and deactivates the local clock source in the repeat mode.

2. The integrated circuit according to claim 1, wherein said local clock source comprises a phase lock loop circuit.

3. The integrated circuit according to claim 1, wherein said wireless transceiver is compliant with IEEE 802.11(n).

4. The integrated circuit according to claim 1 wherein said selector comprises a multiplexer.

5. The integrated circuit according to claim 4 wherein said multiplexer comprises an emitter-follower circuit.

6. The integrated circuit according to claim 1 wherein said clock receiver comprises a programmable impedance circuit configured with a digital to analog converter that controls an impedance of the external clock signal.

7. The integrated circuit according to claim 1 wherein said integrated circuit further comprises connections coupleable to at least one antenna.

8. The integrated circuit according to claim 1 further comprising:

a first terminal that outputs a first polarity of a clock signal; and

a second terminal that outputs a second polarity of the clock signal,

wherein said first terminal and said second terminal are arranged on a common side of a package of the integrated circuit, wherein said first terminal is arranged symmetrical with respect to said second terminal on the common side.

9. A wireless MIMO transceiver comprising the integrated circuit of claim 1.

10. The wireless MIMO transceiver according to claim 9, comprising a plurality of the integrated circuits.

11. The wireless MIMO transceiver according to claim 10, wherein the plurality of the integrated circuits comprise a first integrated circuit and a second integrated circuit connected to the first integrated circuit,

wherein the first integrated circuit operates in the autonomous mode when the second integrated circuit operates in the autonomous mode, and

wherein the first integrated circuit operates in the master mode when the second integrated circuit operates in the slave mode.

12. The wireless MIMO transceiver according to claim 11, wherein the plurality of the integrated circuits further comprise a third integrated circuit coupled between the first integrated circuit and the second integrated circuit,

wherein the third integrated circuit operates in the repeat mode when the first integrated operates in the master mode and the second integrated circuit operates in the slave mode.

13. An integrated circuit comprising:

a clock receiver configured to receive an external clock signal generated external to the integrated circuit;

a local clock source arranged on the integrated circuit and configured to generate a local clock signal;

a selector configured to select one of the external clock signal and the local clock signal;

a clock transmitter configured to transmit the selected one of the external clock signal and the local clock signal; and

a transceiver configured to determine which one of a plurality of modes to operate and further configured to operate in a determined one of the plurality of modes,

wherein the plurality modes comprise;

an autonomous mode in which said selector is activated to select the local clock signal to operate the transceiver based on the selected local clock signal;

a master mode in which said selector and said clock transmitter are activated to select and transmit the local clock signal and to operate the transceiver based on the selected local clock signal;

a slave mode in which said clock receiver and said selector are activated to receive and select the external clock signal and to operate the transceiver based on the selected external clock signal; and

a repeat mode in which said clock receiver, said selector and said clock transmitter are activated to receive, select and transmit the external clock signal and to operate the transceiver based on the selected external clock signal,

wherein the clock receiver and the clock transmitter are deactivated in the autonomous mode, the clock receiver is deactivated in the master mode, the local clock source and the clock transmitter are deactivated in the slave mode, and the local clock source is deactivated in the repeat mode.

14. A method of operating an integrated circuit comprising a wireless transceiver configured to determine which one of a plurality of modes to operate and further configured to operate in a determined one of the plurality of operational modes, the plurality of operational modes comprising an autonomous mode, a master mode, a slave mode and a repeat mode, the method comprising the steps of:

generating a local clock signal internally within the integrated circuit in the autonomous mode and the master mode;

receiving an external clock signal in the slave mode and the repeat mode;

selecting the local clock signal in the autonomous mode and the master mode and the external clock signal in the slave mode and the repeat mode;

transmitting the selected local signal in the master mode and the selected external signal in the slave mode and the repeat mode; and

operating the integrated circuit based on the selected one of the local clock signal and the external clock signal,

wherein the wireless transceiver comprises a clock receiver configured to receive the external clock signal, a local clock source configured to generate the local clock signal, and a clock transmitter configured to transmit one of the external clock signal and the local clock signal,

the method further comprising;

activating the clock receiver to receive the external clock signal in the slave mode and the repeat mode;

activating the local clock source to generate the local clock signal in the autonomous mode and the master mode;

activating the clock transmitter in the master mode and the repeat mode to transmit the local clock signal in the master mode and to transmit the external clock signal in the repeat mode;

deactivating the clock receiver in the autonomous mode and the master mode;

deactivating the local clock source in the slave mode and the repeat mode; and

deactivating the clock transmitter in the autonomous mode and the slave mode.

15. The method according to claim 14, wherein the step of generating a local clock signal comprises generating a local clock signal with a phase lock loop circuit.

16. An integrated circuit comprising:

means for receiving an external clock signal generated external to the integrated circuit;

means for generating a local clock signal arranged on the integrated circuit;

means for selecting one of said external clock signal and said local clock signal;

means for transmitting the selected one of said external clock signal and said local clock signal externally to the integrated circuit;

means for determining one of a plurality of operational modes and operating the integrated circuit in a determined one of the plurality of operational modes, wherein the plurality modes comprise;

an autonomous mode in which said selecting means selects the local clock signal;

a master mode in which said selecting means selects the local clock signal and said transmitting means transmits the selected local clock signal;

a slave mode in which said selecting means selects the external clock signal; and

a repeat mode in which said selecting means selects the external clock signal and said transmitting means transmits the selected external clock signal;

wherein the receiving means is activated in the slave mode and the repeat mode;

wherein the generating means is activated in the autonomous mode and the master mode;

wherein the transmitting means is activated in the master mode and the repeat mode;

wherein the receiving means is deactivated in the autonomous mode and the master mode;

wherein the generating means is deactivated in the slave mode and the repeat mode; and

wherein the transmitting means is deactivated in the autonomous mode and the slave mode.

17. The integrated circuit according to claim 16, wherein said generating means comprises a phase lock loop circuit.

18. The integrated circuit according to claim 16 wherein said selecting means comprises a multiplexer.

19. The integrated circuit according to claim 18 wherein said multiplexer comprises an emitter-follower circuit.

20. The integrated circuit according to claim 16 wherein said receiving means comprises a programmable impedance circuit configured with a digital to analog converter that controls an impedance of the external clock signal.

21. The integrated circuit according to claim 16 further comprising:

a first terminal that outputs a first polarity of a clock signal; and

a second terminal that outputs a second polarity of the clock signal,

wherein said first terminal and said second terminal are arranged on a common side of a package of the integrated circuit, wherein said first terminal is arranged symmetrical with respect to said second terminal on the common side.

22. The integrated circuit according to claim 16 further comprising means for connecting to at least one antenna.

23. A wireless MIMO transceiver comprising the integrated circuit of claim 16.

24. The wireless MIMO transceiver according to claim 23, comprising a plurality of the integrated circuits.

25. The integrated circuit according to claim 24, wherein the plurality of integrated circuits comprise a first integrated circuit and a second integrated circuit connected to the first integrated circuit,

wherein the first integrated circuit operates in the autonomous mode when the second integrated circuit operates in the autonomous mode, and

wherein the first integrated circuit operates in the master mode when the second integrated circuit operates in the slave mode.

26. The integrated circuit according to claim 25, wherein the plurality of the integrated circuits further comprise a third integrated circuit coupled between the first integrated circuit and the second integrated circuit,

wherein the third integrated circuit operates in the repeat mode when the first integrated circuit operates in the master mode and the second integrated circuit operates in the slave mode.

27. The integrated circuit of claim 16, wherein the determining means operate the integrated circuit based on the local clock signal in the autonomous mode and the master mode and operate the integrated circuit based on the external clock signal in the slave mode and the repeat mode.