Memory-daughter-card-testing apparatus and method

• US 7,826,996 B2
• Filed: 02/26/2007
• Issued: 11/02/2010
• Est. Priority Date: 05/20/2003
• Status: Expired due to Fees

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Resnick, David R., Bethard, Roger A., Snyder, Van L., Schwoerer, Gerald A., Grossmeier, Alan M., Marquardt, Kelly J., Steinberger, Michael L.
• Primary Examiner(s): Feliciano; Eliseo Ramos
• Assistant Examiner(s): Huynh; Phuong
• Application Number:
  US11/679,175
• Publication Number:
  US 20080059105A1
• Time in Patent Office: 1,345 Days
• Field of Search: 702118-123, 702180-189, 714733-735, 714/738, 711/115, 710/305, 324/754
• US Class Current: 702/118
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card'"'"'s functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card'"'"'s functions.

Claims

1. A system for using a first memory card to test a second memory card, the system comprising:

a test fixture having a first interface connectable to the first memory card and a second interface connectable to the second memory card, such that at least some inputs from the first interface are connected to corresponding outputs of the second interface, and at least some outputs from the first interface are connected to corresponding inputs of the second interface such that the first memory card can perform write and read operations to the second memory card and the second memory card can perform write and read operations to the first memory card; and

a test controller operable to send configuration data to the first interface to cause a memory-testing function to be performed by the first memory card when suitable first and second memory cards are connected to the fixture, wherein the memory-testing function is configured such that the first memory card sends a plurality of write memory operations and a plurality of read memory operations from the first memory card to the second memory card and the first memory card tests whether the memory operations completed successfully.

2. The system of claim 1, wherein the first interface connects a high-speed SerDes port of the first memory card to a corresponding SerDes port of the second card.

3. The system of claim 1, wherein the test controller receives test results from the first memory card indicative of functionality of the second memory card.

4. The system of claim 1, wherein the test controller includes an interface to send and receive data from respective control interface ports on the first memory card and the second memory card.

5. The system of claim 1, wherein the test controller is operable to configure the second memory card to each one of a plurality of different operation modes.

6. The system of claim 1, further including a test controller connection to both the first and second memory cards.

7. The system of claim 1, wherein the test controller is operable to simultaneously control testing in more than one pair of memory cards, and wherein within each pair, one memory card is used to test the other memory card.

8. A method for testing memory cards, the method comprising:

connecting a plurality of interface lines of a first memory card to corresponding complementary interface lines of a second memory card such that the first memory card can perform write and read operations to the second memory card and the second memory card can perform write and read operations to the first memory card;

configuring the first memory card to be operable to perform testing functions;

configuring the second memory card to be operable to perform normal read and write operations; and

testing the second memory card under the control of the first memory card by sending a plurality of write memory operations and a plurality of read memory operations from the first memory card to the second memory card and the first memory card testing whether the memory operations completed successfully.

9. The method of claim 8, wherein the configuring of the first memory card includes loading microcode into the first memory card.

10. The method of claim 8, wherein the first memory card includes a high-speed SerDes port, the second memory card includes a high-speed SerDes port, and wherein the testing includes sending serial commands and data from the SerDes port of the first memory card to the SerDes port of the second card.

11. The method of claim 8, further comprising sending test results from the first memory card to a test controller external to the first memory cards, the test results indicative of functionality of the second memory card.

12. The method of claim 11, further comprising:

sending control information from the test controller to respective control interface ports on the first memory card and the second memory card.

13. The method of claim 11, further comprising:

configuring the second memory card to each one of a plurality of different operation modes.

14. The method of claim 8, further including a test controller connection to both the first and second memory cards.

15. A non-transitory computer-readable medium having instructions stored thereon that cause a suitably programmed information-processing system to execute a method comprising:

connecting a plurality of interface lines of a first memory card to corresponding complementary interface lines of a second memory card such that the first memory card can perform write and read operations to the second memory card and the second memory card can perform write and read operations to the first memory card;

configuring the first memory card to be operable to perform testing functions on the second memory card;

configuring the second memory card to be operable to perform normal read and write operations; and

testing the second memory card under the control of the first memory card by sending a plurality of write memory operations and a plurality of read memory operations from the first memory card to the second memory card and the first memory card testing whether the memory operations completed successfully.

16. The medium of claim 15, wherein the medium further includes instructions to cause the configuring of the first memory card to include loading microcode into the first memory card.

17. The medium of claim 15, wherein the medium further includes instructions to cause sending of test results from the first memory card to a test controller external to the first memory cards, the test results indicative of functionality of the second memory card.

18. The medium of claim 15, wherein the medium further includes instructions to cause sending of control information from the test controller to respective control interface ports on the first memory card and the second memory card.

19. The medium of claim 15, wherein the medium further includes instructions to cause configuring of the second memory card to each one of a plurality of different operation modes.

20. An apparatus comprising:

a first memory card that includes;

a plurality of memory chips,

a high-speed external card interface connected to write and read data to and from the memory chips,

one or more memory controllers, each one of the one or more memory controllers connected to control a subset of the plurality of memory chips, and

one or more caches, each one of the one or more caches operatively coupled to a corresponding one of the memory controllers; and

a test engine configured to control the high-speed interface and/or the memory chips in order to provide testing functions to a second substantially identical memory card,

wherein the high-speed external card interface further comprises;

a crossbar switch; and

one or more SerDes ports, each one of the one or more SerDes ports connectable through the crossbar switch to a plurality of the caches.