Crystal lookup table generation using neural network-based algorithm

• US 7,827,129 B2
• Filed: 05/18/2007
• Issued: 11/02/2010
• Est. Priority Date: 05/18/2006
• Status: Expired due to Fees

• Current Assignee: Siemens Medical Solutions USA Incorporated (Siemens AG)
• Original Assignee: Siemens Medical Solutions USA Incorporated (Siemens AG)
• Inventors: Atkins, Blake, Lenox, Mark W., Hu, Dongming
• Primary Examiner(s): Sparks; Donald
• Assistant Examiner(s): Fernandez Rivas; Omar F
• Application Number:
  US11/750,554
• Publication Number:
  US 20070271206A1
• Time in Patent Office: 1,264 Days
• Field of Search: 706 14- 18, 706 20- 22, 706 26- 28, 250/363.01, 250/363.02, 250/363.03, 250/363.04, 382/128, 382/130, 382/131, 382155-159
• US Class Current: 706/25
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06T 2207/10016 Video; Image sequence
• CPC Class Codes: G06T 2207/30204 Marker
• CPC Class Codes: G06T 7/80 Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration

Abstract

A crystal lookup table used to define a matching relationship between a signal position of a detected event in a PET scanner and a corresponding detector pixel location is generated using a neural network-based algorithm, and is implemented by a FPGA.

Claims

1. A method for generating a crystal lookup table for use in a nuclear imaging scanner, comprising:

generating a block position profile for a multiplicity of events, the block position profile consisting of X and Y position data of said events;

sequentially reading the X and Y position data of the events in at least one of a histogrammed block position profile for software simulation and on the fly with FPGA hardware implementation;

inputting the X and Y data for each of said events into a self-organizing feature map as an input vector;

defining a weight matrix which represents at least one of neuron positions, and detector pixel locations;

updating the weight matrix for all neurons within a predetermined neighborhood to generate pixel locations; and

following system training, constructing a crystal lookup table using the generated pixel locations.

2. The method of claim 1, wherein neuron a=compet(Wp), W is a weight matrix representing neuron positions, and p is the input vector.

3. The method of claim 1, wherein the step of updating is performed according to the rule W(q)=(1−

α

)w(q−

1)+α

p(q), where α

is a predetermined learning rate and q is a training index number.

4. The method of claim 1, wherein the method is implemented by hardware.

5. The method of claim 4, wherein the method is implemented by a field programmable gate array (FPGA).

6. A self-organizing neural network for generating a crystal lookup table for use in a nuclear imaging scanner, comprising:

a memory for storing data; and

a processor for processing,

an input for receiving a block position profile for a multiplicity of events, the block position profile consisting of X and Y position data of said events and converting said profile into input vectors;

a self-organizing feature map for receiving the X and Y data for each of said events as an input vector;

defining a weight matrix which represents at least one of neuron positions, and detector pixel locations; and

a competitive layer for determining a winning neuron a from said self- organizing feature map, and updating the weight matrix for all neurons within a predetermined neighborhood to generate pixel locations,

wherein the crystal lookup table is generated based on a trained weight vector.

7. The self-organizing neural network of claim 6, wherein neuron a=compet (Wp), W is a weight matrix representing neuron positions, and p is the input vector.

8. The self-organizing neural network of claim 6, wherein the step of updating is performed according to the rule W(q)=(1−

α

)w(q−

1)+α

p(q), where α

is a predetermined learning rate and q is a training index number.

9. The self-organizing neural network of claim 6, wherein the network is implemented on hardware.

10. The self-organizing neural network of claim 9, wherein the hardware comprises a field programmable gate array (FPGA) device.