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Intergrated circuit and a method of cache remapping

  • US 7,827,372 B2
  • Filed: 08/17/2004
  • Issued: 11/02/2010
  • Est. Priority Date: 09/04/2003
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit, comprising:

  • at least one processing unit (PU);

    a cache memory (L2_bank) having a plurality of memory modules for caching data, wherein the cache memory comprises a plurality of distinct physical banks, wherein each physical bank comprises some of the memory modules and is configured to facilitate serving a read/write request independently of other physical banks to allow concurrent transfers for at least two of the physical banks; and

    signal selection circuitry for identifying which memory modules have data cached in said cache memory wherein the signal selection circuitry comprises;

    a Tag RAM unit (TagRAM) to generate a hit signal based on an input address, wherein the hit signal is indicative of an originally mapped way for data corresponding to the input address; and

    remapping means (RM, MapRAM) for performing a remapping within said plurality of memory modules, wherein the remapping permits remapping the memory modules from a first physical bank of memory modules to a second physical bank of memory modules, wherein the remapping means is configured to generate a hit'"'"' signal based on the hit signal from the Tag RAM unit, wherein the hit'"'"' signal is indicative of a remapped way for the data corresponding to the input address.

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