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Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs

  • US 7,827,519 B2
  • Filed: 10/02/2007
  • Issued: 11/02/2010
  • Est. Priority Date: 12/29/2006
  • Status: Active Grant
First Claim
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1. A machine implemented method for integrating three-dimensional integrated circuits, comprising:

  • using at least a computer system which comprises at least one processor and is programmed for performing;

    identifying an electronic circuit design for an electronic circuit;

    identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level;

    identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer;

    identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit;

    determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level;

    determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and

    displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium.

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