Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
First Claim
1. A machine implemented method for integrating three-dimensional integrated circuits, comprising:
- using at least a computer system which comprises at least one processor and is programmed for performing;
identifying an electronic circuit design for an electronic circuit;
identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level;
identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer;
identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit;
determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level;
determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and
displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium.
1 Assignment
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Accused Products
Abstract
Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.
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Citations
25 Claims
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1. A machine implemented method for integrating three-dimensional integrated circuits, comprising:
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using at least a computer system which comprises at least one processor and is programmed for performing; identifying an electronic circuit design for an electronic circuit; identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level; identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer; identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit; determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level; determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A system for integrating three-dimensional integrated circuits, comprising:
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at least one computer system that comprises at least one processor and is programmed for performing; identifying an electronic circuit design for an electronic circuit; identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level; identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer; identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit; determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level; determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium. - View Dependent Claims (23)
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24. A computer program product comprising a computer-usable storage non-transitory medium having executable code which, when executed by at least one computer system, causes the at least one computer system to execute a process for integrating three-dimensional integrated circuits, the process comprising:
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using at least a computer system which comprises at least one processor and is programmed for performing; identifying an electronic circuit design for an electronic circuit; identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level; identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer; identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit; determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level; determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium. - View Dependent Claims (25)
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Specification