Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs

• US 7,827,519 B2
• Filed: 10/02/2007
• Issued: 11/02/2010
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., White, David
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/866,385
• Publication Number:
  US 20080163139A1
• Time in Patent Office: 1,127 Days
• Field of Search: 716/1, 716/2, 716/4, 716/5, 716/8, 716/10, 716/13, 716/19
• US Class Current: 716/54
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.

Claims

1. A machine implemented method for integrating three-dimensional integrated circuits, comprising:

using at least a computer system which comprises at least one processor and is programmed for performing;

identifying an electronic circuit design for an electronic circuit;

identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level;

identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer;

identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit;

determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level;

determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and

displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium.

2. The machine implemented method of claim 1, further comprising:

determining a process or technique for preparing the second semiconductor substrate layer by analyzing the second semiconductor substrate layer in conjunction with an additional concurrent model for the process or technique.

3. The machine implemented method of claim 2, in which the process or technique for preparing the second semiconductor substrate layer comprises an UV-Cl₂ cleaning process, an UV-03 cleaning process, or a planarization process.

4. The machine implemented method of claim 1, in which the determining whether the second semiconductor substrate layer meets a criterion to receive the second level further comprising:

identifying a process which causes the second semiconductor substrate layer to be created between the insulating dielectric layer (IDL) and the second level of the electronic circuit.

5. The machine implemented method of claim 4, in which the second semiconductor substrate layer comprises a polycrystalline silicon layer, a single crystalline silicon layer, or other semiconductor layer.

6. The machine implemented method of claim 4, in which the process comprises CVD low temperature epitaxial growth process, low temperature electron beam or laser induced re-crystallization process of the polysilicon, a metal induced lateral crystallization process, or a low temperature deposition and crystallization of amorphous silicon process.

7. The machine implemented method of claim 1, in which the determining whether the second semiconductor substrate layer meets a criterion further comprising:

determining a buffer layer process which causes a buffer layer to be created atop the second semiconductor substrate layer based upon a concurrent model for the buffer layer process, the buffer layer comprises a germanium layer, a silicon-germanium layer, or an inter-layer dielectric (ILD) layer.

8. The machine implemented method of claim 7, in which the buffer layer process comprises an epitaxial growth process, a deposition process, a dry cleaning process, an UV-Cb cleaning process, or an UV-03 cleaning process.

9. The machine implemented method of claim 7, further comprising:

determining whether the buffer layer meets a second criterion to receive the second level of the electronic circuit, wherein the second criterion comprise a performance, manufacturability, or reliability requirement for the second level of the electronic design or for the electronic design.

10. The machine implemented method of claim 1, in which the determining whether the second semiconductor substrate layer meets a criterion further comprises:

analyzing the second semiconductor substrate layer or an underlying structure of the second semiconductor substrate layer, in which the underlying structure comprises the first level of the electronic circuit or the first semiconductor substrate layer.

11. The machine implemented method of claim 10, in which the analyzing act comprises determining an attribute of a top surface or content of the second semiconductor substrate layer or of its underlying structure.

12. The machine implemented method of claim 11, in which the attribute comprises flatness, roughness, or integrity of the top surface of the second semiconductor substrate layer or composition, species, stress, strain, or bulk property or distribution of species within the second semiconductor substrate layer or within the IDL.

13. The machine implemented method of claim 1, in which the determining whether the second semiconductor substrate layer meets a criterion further comprises:

determining a parameter to cause the second semiconductor substrate layer to be created atop the insulating dielectric layer (IDL).

14. The machine implemented method of claim 1, in which the determining whether the second semiconductor substrate layer meets a criterion comprises:

determining parameter of a process which causes the second semiconductor substrate layer to be created atop the IDL based upon a concurrent model for the process.

15. The machine implemented method of claim 1, in which the identifying a process which causes an insulating dielectric layer to be created comprises:

determining a parameter for a process creating the insulating dielectric layer (IDL) based upon the first concurrent model for the first level of the electronic circuit.

16. The machine implemented method of claim 1, in which the identifying a process which causes an insulating dielectric layer to be created comprises:

analyzing a structure underlying the insulating dielectric layer (IDL), in which the structure comprise the first level of the electronic circuit or the first semiconductor substrate layer.

17. The machine-implemented method of claim 1, in which a portion of the electronic circuit design is generated by context simulation method.

18. The machine-implemented method of claim 1, further comprising:

causing to manufacture a portion of the electronic circuit, in which a design for the portion of the electronic circuit is generated by context simulation method.

19. The machine implemented method of claim 1, further comprising:

determining whether the second semiconductor substrate layer meets a second criterion to receive at least a part of the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level.

20. The machine implemented method of claim 1, further comprising:

causing the second semiconductor substrate layer to be manufactured on the IDL.

21. The machine implemented method of claim 20, the act of causing the second semiconductor substrate comprising:

preparing the IDL for the second semiconductor substrate layer by using at least the first concurrent model or a result generated by the first concurrent model for the first level and one or more additional concurrent models for the IDL or the second semiconductor substrate layer.

22. A system for integrating three-dimensional integrated circuits, comprising:

at least one computer system that comprises at least one processor and is programmed for performing;

identifying an electronic circuit design for an electronic circuit;

identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level;

identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer;

identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit;

determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level;

determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and

displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium.

23. The system of claim 22, the at least one computer system is further programmed for performing:

determining whether the second semiconductor substrate layer meets a second criterion to receive at least a part of the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level.

24. A computer program product comprising a computer-usable storage non-transitory medium having executable code which, when executed by at least one computer system, causes the at least one computer system to execute a process for integrating three-dimensional integrated circuits, the process comprising:

using at least a computer system which comprises at least one processor and is programmed for performing;

identifying an electronic circuit design for an electronic circuit;

identifying a first concurrent model for a first process or technique for manufacturing a first level of the electronic circuit, the first level comprising a first semiconductor substrate layer, wherein the first concurrent model at least predicts a topographical characteristic of the first level;

identifying a second level of the electronic design, the second level comprising a second semiconductor substrate layer;

identifying a process which causes an insulating dielectric layer (IDL) to be created between the first level and the second level of the electronic circuit;

determining whether the IDL meets a criterion to receive the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level;

determining a location on the IDL for a via or an interconnection connecting the first level and the second level of the electronic circuit; and

displaying the electronic circuit design or storing the electronic circuit design in a tangible machine accessible storage non-transitory medium.

25. The computer program product of claim 24, the process further comprising:

determining whether the second semiconductor substrate layer meets a second criterion to receive at least a part of the second level of the electronic circuit by using at least the first concurrent model or a result generated by the first concurrent model for the first level.