Semiconductor device and manufacturing method of the same

• US 7,829,394 B2
• Filed: 05/16/2006
• Issued: 11/09/2010
• Est. Priority Date: 05/26/2005
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Takano, Tamae
• Primary Examiner(s): Nguyen; Khiem D
• Application Number:
  US11/434,163
• Publication Number:
  US 20060267099A1
• Time in Patent Office: 1,638 Days
• Field of Search: 438149-155, 257/E51.005, 257/E51.006
• US Class Current: 438/149
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device

Abstract

The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions.

Claims

1. A manufacturing method of a semiconductor device comprising:

forming a semiconductor film over a substrate;

forming a gate insulating film over the semiconductor film;

forming a gate electrode selectively over the semiconductor film with the gate insulating film interposed therebetween;

forming selectively a first resist to cover a portion of the gate electrode and a portion of the semiconductor film, and then forming a first impurity region selectively in the semiconductor film by adding a first impurity element selectively to the semiconductor film using the first resist as a first mask, wherein the first impurity region is in direct physically contact with a portion of the semiconductor film which is located directly under the first resist;

removing the first mask;

forming a second impurity region selectively in the semiconductor film by adding a second impurity element selectively to the semiconductor film using the gate electrode as a second mask;

forming side wall spacers adjacent to sides of the gate electrode;

forming a second resist to cover a portion of the gate electrode and a portion of the semiconductor film, and forming a third impurity region selectively by adding a third impurity element selectively to the semiconductor film using the second resist as a third mask, after forming the side wall spacers;

forming an insulating film over the gate electrode and the gate insulating film; and

forming a conductive film over the insulating film, wherein the conductive film is electrically connected with the semiconductor film.

2. The manufacturing method of a semiconductor device according to claim 1, wherein an impurity element of p-type conductivity is used as the first impurity element, and an impurity element of n-type conductivity is used as the second impurity element and the third impurity element.

3. The manufacturing method of a semiconductor device according to claim 1, wherein a concentration of the second impurity element is lower than a concentration of the third impurity element.

4. A manufacturing method of a semiconductor device comprising:

forming a semiconductor film over a substrate;

forming a gate insulating film over the semiconductor film;

forming a first gate electrode and a second gate electrode over the semiconductor film with the gate insulating film interposed therebetween;

forming selectively a first resist to cover the first gate electrode and a portion of the semiconductor film, and then forming a first impurity region selectively in the semiconductor film by adding a first impurity element selectively to the semiconductor film using the first resist as a first mask, wherein the first impurity region is in direct physically contact with a portion of the semiconductor film which is located directly under the first resist;

removing the first mask;

forming a second impurity region selectively in the semiconductor film by adding a second impurity element selectively to the semiconductor film using the first gate electrode and the second gate electrode as a second mask;

forming side wall spacers adjacent to sides of the first gate electrode and the second gate electrode;

forming a second resist to cover the second gate electrode and a portion of the semiconductor film, and forming a third impurity region selectively by adding a third impurity element selectively to the semiconductor film using the second resist as a third mask, after forming the side wall spacers;

forming an insulating film over the first gate electrode, the second gate electrode and the gate insulating film; and

forming a conductive film over the insulating film, wherein the conductive film is electrically connected with the semiconductor film.

5. The manufacturing method of a semiconductor device according to claim 4, wherein an impurity element of p-type conductivity is used as the first impurity element, and an impurity element of n-type conductivity is used as the second impurity element and the third impurity element.

6. The manufacturing method of a semiconductor device according to claim 4, wherein a concentration of the second impurity element is lower than a concentration of the third impurity element.

7. A manufacturing method of a semiconductor device comprising:

forming a semiconductor film over a substrate;

forming a gate insulating film over the semiconductor film;

forming a gate electrode selectively over the semiconductor film with the gate insulating film interposed therebetween;

forming selectively a first resist to cover a portion of the gate electrode and a portion of the semiconductor film, and then forming a first impurity region selectively in the semiconductor film by adding a first impurity element selectively to the semiconductor film using the first resist as a first mask, wherein the first impurity region is in direct physically contact with a portion of the semiconductor film which is located directly under the first resist;

removing the first mask;

forming a second impurity region selectively in the semiconductor film by adding a second impurity element selectively to the semiconductor film using the gate electrode as a second mask;

forming side wall spacers adjacent to sides of the gate electrode; and

forming a second resist to cover a portion of the gate electrode and a portion of the semiconductor film, and forming a third impurity region selectively by adding a third impurity element selectively to the semiconductor film using the second resist as a third mask, after forming the side wall spacers.

8. The manufacturing method of a semiconductor device according to claim 7, wherein an impurity element of p-type conductivity is used as the first impurity element, and an impurity element of n-type conductivity is used as the second impurity element and the third impurity element.

9. The manufacturing method of a semiconductor device according to claim 7, wherein a concentration of the second impurity element is lower than a concentration of the third impurity element.

10. A manufacturing method of a semiconductor device comprising:

forming a semiconductor film over a substrate;

forming a gate insulating film over the semiconductor film;

forming a first gate electrode and a second gate electrode over the semiconductor film with the gate insulating film interposed therebetween;

forming selectively a first resist to cover the first gate electrode and a portion of the semiconductor film, and then forming a first impurity region selectively in the semiconductor film by adding a first impurity element selectively to the semiconductor film using the first resist as a first mask, wherein the first impurity region is in direct physically contact with a portion of the semiconductor film which is located directly under the first resist;

removing the first mask;

forming a second impurity region selectively in the semiconductor film by adding a second impurity element selectively to the semiconductor film using the first gate electrode and the second gate electrode as a second mask;

forming side wall spacers adjacent to sides of the first gate electrode and the second gate electrode; and

forming a second resist to cover the second gate electrode and a portion of the semiconductor film, and forming a third impurity region selectively by adding a third impurity element selectively to the semiconductor film using the second resist as a third mask, after forming the side wall spacers.

11. The manufacturing method of a semiconductor device according to claim 10, wherein an impurity element of p-type conductivity is used as the first impurity element, and an impurity element of n-type conductivity is used as the second impurity element and the third impurity element.

12. The manufacturing method of a semiconductor device according to claim 10, wherein a concentration of the second impurity element is lower than a concentration of the third impurity element.