Edge connect wafer level stacking

• US 7,829,438 B2
• Filed: 04/13/2007
• Issued: 11/09/2010
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage
• Primary Examiner(s): Bryant; Kiesha R
• Assistant Examiner(s): Wagner; Jenny L
• Application Number:
  US11/787,209
• Publication Number:
  US 20080083977A1
• Time in Patent Office: 1,306 Days
• Field of Search: 438/462, 438/109, 257/E23.179
• US Class Current: 438/462
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

Claims

1. A method of manufacturing a stacked microelectronic package comprising the steps of:

(a) forming a first element including a first wafer and a second wafer overlying the first wafer, each of the first and second wafers including a plurality of microelectronic elements, a plurality of first saw lanes extending in a first direction and a plurality of second saw lanes extending in a second direction transverse to the first direction, a given first saw lane of the second wafer being aligned with and positioned above a given saw lane of the first wafer,

wherein the plurality of first saw lanes and the plurality of second saw lanes extend between adjacent ones of the microelectronic elements of each wafer, at least one microelectronic element has a plurality of contacts exposed at a face of the first wafer or of the second wafer and a plurality of metal traces electrically connected with respective ones of the contacts and extending toward the aligned first saw lanes, and the first element further includes an insulating region extending in the first direction and aligned with the aligned first saw lanes;

(b) forming at least one opening in the insulating region in alignment with the aligned first saw lanes, each at least one opening exposing no more than a single trace of the plurality of traces of the at least one microelectronic element;

(c) forming a lead within the at least one opening, the lead being electrically connected to no more than a single trace of the at least one microelectronic element; and

(d) severing the first and the second wafers along the aligned first saw lanes and through the insulating regions into a plurality of assemblies, each assembly including a plurality of stacked microelectronic elements and exposed leads.

2. The method as claimed in claim 1, wherein the at least one opening exposes no more than a single trace of a first microelectronic element of the first wafer and no more than a single trace of a second microelectronic element of the second wafer.

3. The method as claimed in claim 1, wherein the leads include first ends overlying a face of one of the first and the second wafers.

4. The method as claimed in claim 3, wherein the first ends of the leads include conductive bumps.

5. The method as claimed in claim 1, wherein the at least one opening includes a plurality of openings in alignment with the aligned first saw lanes and spaced apart in the first direction, each of the plurality of openings being insulated from each other opening of the plurality of openings.

6. The method as claimed in claim 5, wherein step (c) includes forming conductors, each conductor contacting an exposed trace within one of the plurality of openings, and step (d) includes severing the conductors along the aligned first saw lane, such that the leads include severed portions of the conductors.

7. The method as claimed in claim 6, wherein the forming of the conductors includes depositing a conductive material within the openings.

8. The method as claimed in claim 6, wherein the forming of the conductors includes filling the openings with a metal.