Through-wafer vias

• US 7,829,462 B2
• Filed: 05/03/2007
• Issued: 11/09/2010
• Est. Priority Date: 05/03/2007
• Status: Expired due to Fees

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Licensing, LLC
• Inventors: DeNatale, Jeffrey F., Lauxtermann, Stefan C.
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Naraghi, Ali
• Application Number:
  US11/800,098
• Publication Number:
  US 20080272499A1
• Time in Patent Office: 1,286 Days
• Field of Search: 257/758, 438/667
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removeably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

Claims

1. A method of making a circuit portion, comprising:

providing a wafer that includes a substrate;

defining a portion of the wafer as the circuit portion;

fabricating active semiconducting devices in the circuit portion;

depositing an electrically insulating layer on the substrate;

depositing an electrically conducting metal layer on the insulating layer;

fabricating a plurality of semiconducting devices in the layers; and

defining a through-wafer via interconnect region within the circuit portion, the through-wafer via interconnect region having removeably distributed metal in the conducting metal layer whereby dishing is prevented between the through-wafer via interconnection region and the remainder of the circuit portion;

wherein the electrically conducting metal layer is a first electrically conducting metal layer and the electrically insulating layer is a first electrically insulating layer, further comprising;

depositing a second electrically insulating layer on the first electrically conducting metal layer;

depositing a second electrically conducting metal layer on the second insulating layer; and

depositing a third electrically insulating layer on the second electrically conducting metal layer;

forming a plurality of metal interconnects within the through-via interconnect region, each metal interconnect extending through the second insulating layer between the first metal layer and the second metal layer;

removing the third insulating layer within the through-via interconnect region;

removing the metal in the second metal layer within the through-via interconnect region;

removing the metal interconnects between the first and second metal layers;

removing the second insulating layer within the through-via interconnect region;

removing the metal in the first metal layer within the through-via interconnect region;

removing the first insulating layer within the through-via interconnect region;

removing the substrate within the through-via interconnect region;

electrically isolating the periphery of the through-via interconnect region; and

filling the through-via interconnect region with an electrically conducting metal, thereby creating a through-wafer via interconnect in the circuit portion.

2. The method of claim 1, wherein depositing an electrically insulating layer comprises depositing a dielectric layer.

3. The method of claim 1, further comprising:

dicing the wafer to separate the circuit portion, thereby rendering the circuit portion usable as a layer in a vertically stacked three dimensional integrated circuit.