Quantum photonic imagers and methods of fabrication thereof

• US 7,829,902 B2
• Filed: 06/17/2009
• Issued: 11/09/2010
• Est. Priority Date: 09/27/2007
• Status: Expired due to Fees

• Current Assignee: Ostendo Technologies Inc.
• Original Assignee: Ostendo Technologies Inc.
• Inventors: El-Ghoroury, Hussein S., McNeill, Dale A., Brown, Robert G. W., DenBoer, Huibert, Lanzone, Andrew J.
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Abdelaziez; Yasser A
• Application Number:
  US12/486,600
• Publication Number:
  US 20090278998A1
• Time in Patent Office: 510 Days
• Field of Search: 372/8, 372/22, 372/38, 372/42, 372/50.1, 372/50.121, 372/50.122, 372/50.124, 345/84
• US Class Current: 257/89
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2340/06 Colour space transformation
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: H01S 5/02345 Wire-bonding
• CPC Class Codes: H01S 5/18 Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
• CPC Class Codes: H01S 5/2009 by using electron barrier layers
• CPC Class Codes: H01S 5/3063 using Mg
• CPC Class Codes: H01S 5/34326 with a well layer based on InGa(Al)P, e.g. red laser
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
• CPC Class Codes: H01S 5/4043 with vertically stacked active layers
• CPC Class Codes: H01S 5/4093 Red, green and blue [RGB] generated directly by laser action or by a combination of laser action with nonlinear frequency conversion
• CPC Class Codes: H04N 9/3161 using laser light sources using laser beams scanning the display screen H04N9/3129

Abstract

Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Claims

1. A digital semiconductor structure for bonding to a two-dimensional multicolor light emitting pixel array comprising:

multiple two dimensional arrays of pixel logic cells;

a digital control logic region positioned at the periphery of the array of pixels logic cells;

a plurality of device contact pads positioned at the periphery of the digital control logic region; and

a plurality of metal layers configured to;

interconnect the array of pixels logic cells with the digital control logic region;

connect the digital control logic region with the plurality of the device contact pads; and

interconnect the array of pixel logic cells with a two-dimensional multicolor light emitting pixel array.

2. The structure of claim 1 wherein the top metal layer is comprised of an array of pixel contact pads patterned to match a two-dimensional multicolor light emitting pixel array to be bonded thereto.

3. The structure of claim 2 wherein one metal layer comprises a plurality of separate power and ground rails for distributing power and ground to:

the digital control logic region;

the array of pixels logic cells; and

a two-dimensional multicolor light emitting pixel array to be bonded to the pixel contact pads.

4. The structure of claim 3 wherein one metal layer comprises a plurality metal traces for distributing data, update and clear signals to the pixels logic cells.

5. The structure of claim 4 wherein one metal layer comprises a plurality of separate metal traces for distributing the load and enable signals to the pixels logic cells.

6. The structure of claim 5 wherein each two dimensional array of pixel logic cells comprise a plurality of logic circuits that:

gate power to respective pixel contact pads in response to an enable signal generated by the digital control logic region;

and latch the next on-off states of the respective pixel contact pads for one color of a two-dimensional multicolor light emitting pixel array to be bonded thereto in response to load signals generated by the digital control logic region.

7. The structure of claim 6 wherein the plurality of logic circuits each:

generate the enable and load signals for each respective pixel logic cell in response to a serial bit stream input provided by a companion device that defines the on-off states of the respective pixel contact pads of a two-dimensional multicolor light emitting pixel array to be bonded thereto within a duration of an input clock period, the serial bit stream and clock inputs being routed to the digital control logic region via the plurality of device contact pads.

8. A digital semiconductor structure for bonding to a two-dimensional light emitting pixel array comprising:

at least one two dimensional array of pixel logic cells;

a digital control logic region positioned at the periphery of the array of pixels logic cells;

a plurality of device contact pads positioned at the periphery of the digital control logic region; and

a plurality of metal layers configured to;

interconnect the array of pixels logic cells with the digital control logic region;

connect the digital control logic region with the plurality of the device contact pads; and

interconnect the array of pixel logic cells with a two-dimensional light emitting pixel array.

9. The structure of claim 8 wherein the top metal layer is comprised of an array of pixel contact pads patterned to match a two-dimensional light emitting pixel array to be bonded thereto.

10. The structure of claim 9 wherein one metal layer comprises a plurality of separate power and ground rails for distributing power and ground to:

the digital control logic region;

the array of pixels logic cells; and

a two-dimensional light emitting pixel array to be bonded to the pixel contact pads.

11. The structure of claim 10 wherein one metal layer comprises a plurality metal traces for distributing data, update and clear signals to the pixels logic cells.

12. The structure of claim 11 wherein one metal layer comprises a plurality of separate metal traces for distributing the load and enable signals to the pixels logic cells.

13. The structure of claim 12 wherein each two dimensional array of pixel logic cells comprise a plurality of logic circuits that:

gate power to respective pixel contact pads in response to an enable signal generated by the digital control logic region;

and latch the next on-off states of the respective pixel contact pads for one color of a two-dimensional light emitting pixel array to be bonded thereto in response to load signals generated by the digital control logic region.

14. The structure of claim 13 wherein the plurality of logic circuits each:

generate the enable and load signals for each respective pixel logic cell in response to a serial bit stream input provided by a companion device that defines the on-off states of the respective pixel contact pads of a two-dimensional light emitting pixel array to be bonded thereto within a duration of an input clock period, the serial bit stream and clock inputs being routed to the digital control logic region via the plurality of device contact pads.