Microelectronic devices and methods for forming interconnects in microelectronic devices

• US 7,829,976 B2
• Filed: 04/06/2009
• Issued: 11/09/2010
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Hembree, David R., Kirby, Kyle K., Rigg, Sidney B., Akram, Salman, Hiatt, William M.
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US12/419,029
• Publication Number:
  US 20090191701A1
• Time in Patent Office: 582 Days
• Field of Search: 257/621, 257/E23.141
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/0305 Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
• CPC Class Codes: H05K 2201/09827 Tapered, e.g. tapered hole, via or groove
• CPC Class Codes: H05K 2203/072 Electroless plating, e.g. finish plating or initial plating
• CPC Class Codes: H05K 2203/1147 : Sealing or impregnating, e.g. of pores
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 3/422 : characterised by electroless plating method; pretreatment therefor
• CPC Class Codes: H05K 3/423 : characterised by electroplating method

Abstract

Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Claims

1. A semiconductor die having an integrated circuit and a terminal electrically coupled to the integrated circuit, the semiconductor die comprising:

a passage extending completely through the terminal and the die;

a conductive cap in physical and electrical contact with the terminal; and

a conductive fill material in the passage and in contact with the conductive cap,

wherein the conductive cap is formed prior to filling the passage with the conductive fill material and closes off an opening at an end of the passage adjacent to the terminal without completely filling the passage.

2. The semiconductor die of claim 1 wherein the conductive cap comprises a gold stud bump.

3. The semiconductor die of claim 1 wherein the conductive cap comprises a solder ball.

4. The semiconductor die of claim 1 wherein the conductive cap comprises an aluminum wedge.

5. The semiconductor die of claim 1 wherein the conductive cap comprises Ni applied using an electroless plating procedure.

6. The semiconductor die of claim 1, further comprising a dielectric liner disposed on the sidewalls of the passage, and wherein the conductive fill material is over at least a portion of the dielectric liner.

7. The semiconductor die of claim 1 wherein the conductive fill material comprises electrolytic nickel, electrolytic copper, electrolytic solder, electroless nickel, electroless copper, conductive polymer paste, and/or molten solder.

8. A semiconductor die having integrated circuitry and a bond-pad electrically coupled to the integrated circuitry, the semiconductor die comprising:

a via aligned with the bond-pad and extending completely through the bond-pad and the die;

a conductive cap in contact with the bond-pad and pinching off an end of the via at the bond-pad; and

a conductive material in the via and in contact with the conductive cap, wherein the conductive material is disposed in the via after the conductive cap pinches off the end of the via at the bond-pad.

9. The semiconductor die of claim 8, further comprising a dielectric material coating the sidewalls of the passage, and wherein the conductive material is deposited over at least a portion of the dielectric material.

10. The semiconductor die of claim 8 wherein the conductive cap comprises an aluminum wedge stud.

11. The semiconductor die of claim 8 wherein the conductive cap comprises a solder cap.

12. The semiconductor die of claim 8 wherein the conductive cap comprises copper, palladium, and/or solder.

13. A method of forming an interconnect in a semiconductor die, the semiconductor die including a substrate, integrated circuitry, and a terminal at a front side of the substrate and electrically coupled to the substrate, the method comprising:

forming a passage extending through the substrate and the terminal, wherein the passage has an opening at the terminal;

occluding the opening with a conductive cap that is in electrical contact with the terminal; and

depositing a conductive fill material into the passage and in contact with the conductive cap after occluding the opening with the conductive cap.

14. The method of claim 13 wherein occluding the opening with the conductive cap comprises using an electroless plating technology to seal the opening of the passage at the terminal.

15. The method of claim 13 wherein occluding the opening with the conductive cap comprises applying Ni in an electroless plating process to seal the opening of the passage at the terminal.

16. The method of claim 13 wherein occluding the opening with the conductive cap comprises depositing a stud bump to seal the opening of the passage at the terminal.

17. The method of claim 13 wherein occluding the opening with the conductive cap comprises:

depositing a solder ball, solder paste, and/or solder perform at least proximate to the terminal and the opening; and

reflowing the solder material to form the conductive cap and seal the opening of the passage at the terminal.

18. The method of claim 13 wherein depositing a conductive fill material into the passage comprises:

positioning a conductive member adjacent to the front side of the substrate and in electrical contact with the conductive cap; and

electrically biasing the conductive cap at a potential with the conductive member to electroplate the conductive fill material into the passage.

19. The method of claim 13 wherein depositing a conductive fill material into the passage comprises filling the passage with electrolytic nickel, electrolytic copper, electrolytic solder, electroless nickel, electroless copper, conductive polymer paste, and/or molten solder.

20. The method of claim 13, further comprising applying a dielectric liner to at least a portion of the passage before occluding the opening with the conductive cap.

21. The method of claim 13 wherein forming a passage extending through the substrate and the terminal comprises using a laser-cutting process to form the passage extending through the substrate and the terminal.

22. The method of claim 13 wherein forming a passage extending through the substrate and the terminal comprises using an etching process to form the passage extending through the substrate and the terminal.