Closed loop CESL high performance CMOS device
First Claim
Patent Images
1. A semiconductor device comprising:
- a substrate with a recess formed in a source/drain region of said substrate;
at least one gate structure on said substrate, the gate structure comprising a gate electrode;
at least one “
L-like”
shaped layer having a first leg immediately adjacent to the gate electrode and extending to a first end along the gate electrode, and a second leg extending to a second end along said substrate, said at least one “
L-like”
shaped layer being formed of a single, metal-containing first material;
at least one spacer in contact with said first and second legs of said at least one “
L-like”
shaped layer; and
an intrinsically stressed layer covering said at least one gate structure, said at least one “
L-like”
shaped layer, said at least one spacer, and selected areas of said substrate, said intrinsically stressed layer in contact with said first and second ends of said “
L-like”
shaped layer, the intrinsically stressed layer being formed of the single, metal-containing first material.
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Abstract
An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
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Citations
18 Claims
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1. A semiconductor device comprising:
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a substrate with a recess formed in a source/drain region of said substrate; at least one gate structure on said substrate, the gate structure comprising a gate electrode; at least one “
L-like”
shaped layer having a first leg immediately adjacent to the gate electrode and extending to a first end along the gate electrode, and a second leg extending to a second end along said substrate, said at least one “
L-like”
shaped layer being formed of a single, metal-containing first material;at least one spacer in contact with said first and second legs of said at least one “
L-like”
shaped layer; andan intrinsically stressed layer covering said at least one gate structure, said at least one “
L-like”
shaped layer, said at least one spacer, and selected areas of said substrate, said intrinsically stressed layer in contact with said first and second ends of said “
L-like”
shaped layer, the intrinsically stressed layer being formed of the single, metal-containing first material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising a substrate having a first recess and a second recess located within the substrate:
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a first device on the substrate adjacent the first recess, the first device comprising a gate electrode, at least one “
L-like”
shaped layer in contact with the gate electrode, and a first spacer in contact with said at least one “
L-like”
shaped layer;a second device on the substrate adjacent the second recess having at least one offset spacer and a second spacer in contact with said offset spacer; and an intrinsically stressed layer covering said first device, said second device, said first spacer, said second spacer and in contact with said at least one “
L-like”
shaped layer, said at least one “
L-like”
shaped layer and the intrinsically stressed layer being formed of only a metal-based high-k first material. - View Dependent Claims (17, 18)
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Specification