Stackable ceramic FBGA for high thermal applications

• US 7,829,991 B2
• Filed: 10/18/2007
• Issued: 11/09/2010
• Est. Priority Date: 06/30/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J., Kinsman, Larry D., Moden, Walter L., Mess, Leonard E.
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US11/874,531
• Publication Number:
  US 20080042252A1
• Time in Patent Office: 1,118 Days
• Field of Search: 257/E23.023, 257/686, 257/685, 257/687, 257/698, 257/723, 257/725, 257730-733, 257/737, 257/777, 438/109, 438/613
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Claims

1. An assembly using a stackable FBGA comprising:

a first carrier having a plurality of sides, having an upper surface, having a bottom surface, having a cavity extending from the upper surface, a first frusto-conical surface on a portion of the upper surface thereof, a second frusto-conical surface on a portion of the bottom surface thereof, a lip on a portion of a bottom surface thereof, and a plurality of circuits located within a portion of the cavity;

a semiconductor device having a plurality of bond pads located within the cavity of the first carrier;

a first connector between at least one circuit of the plurality of circuits located within the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

a second connector material located within the first carrier.

2. The assembly using a stackable FBGA of claim 1, further comprising:

a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof; and

at least one second connector connected to the second connector material in the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

3. The assembly using a stackable FBGA of claim 1, wherein the first carrier includes at least one fin on a portion thereof.

4. The assembly of claim 1, further comprising:

a second carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located within a portion of the cavity thereon connected to the at least one aperture therethrough;

a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

another first connector between at least one circuit of the plurality of circuits located within the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier;

encapsulant material filling the portion of the cavity in the second carrier; and

a connector material located within a second aperture in the second carrier connected to the second connector material in the at least one aperture in the first carrier.

5. An assembly for use with a FBGA substrate comprising:

a first carrier having a first surface having a first frusto-conical surface and at least one connection pad thereon, having a second surface having a lip, a second frusto-conical surface connected to the lip, and at least one connection pad thereon, having a cavity extending from the upper surface therein, a first surface located in the cavity having at least one connection pad thereon, a second surface located in the cavity having at least one connection pad thereon, and a third surface located in the cavity, a circuit connecting the at least one connection pad on the first surface of the first carrier to the at least one connection pad on the second surface of the first carrier, and at least one circuit located in a portion of the cavity connected to the at least one connection pad on one of the first surface located in the cavity and the second surface located in the cavity, the at least one connection pad on the first surface of the first carrier, and the at least one connection pad on the second surface of the first carrier;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located on the third surface located in the cavity of the first carrier;

a first connector between the at least one connection pad on one of the first surface located in the cavity and the second surface located in the cavity and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

6. The assembly of claim 5, further comprising:

a substrate having a first surface, a second surface, and at least one circuit on the first surface thereof; and

at least one second connector connected to the at least one connection pad on the second surface of the first carrier and the at least one circuit on the first surface of the substrate.

7. The assembly of claim 5, wherein the first carrier includes at least one fin on a portion thereof.

8. The assembly of claim 5, further comprising:

a second carrier having a cavity therein, a first surface, a second surface, at least one connection pad on the first surface, at least one connection pad on the second surface, a circuit connecting the at least one connection pad on the first surface to the at least one connection pad on the second surface, and at least one circuit located in a portion of the cavity and connected to one of the at least one connection pad on the first surface and the at least one connection pad on the second surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one circuit located in a portion of the cavity of the second carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the second carrier.

9. An assembly of stacked carriers for use with a substrate comprising:

a first carrier having a first frusto-conical surface on a portion of an upper surface thereof, a second frusto-conical surface on a portion of a bottom surface thereof, a lip on a portion of the bottom surface thereof, and a plurality of circuits located within a portion of a cavity having a first surface, a second surface, and a third surface, a connection pad located on one of the first surface and the second surface connected to at least one of the plurality of circuits;

a semiconductor device having a plurality of bond pads located on a portion of the third surface within the cavity of the first carrier;

a first connector between at least one circuit of the plurality of circuits located within the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

a second connector material located within the first carrier.

10. The assembly of stacked carriers for use with a substrate of claim 9, wherein the substrate includes an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof, and at least one second connector connected to the second connector material in the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

11. The assembly of stacked carriers for use with a substrate of claim 9, wherein the first carrier includes a heat sink on a portion thereof.

12. The assembly of claim 9, further comprising:

a second carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located within a portion of the cavity thereon connected to the at least one aperture therethrough;

a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

another first connector between at least one circuit of the plurality of circuits located within the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier;

encapsulant material filling the portion of the cavity in the second carrier; and

a connector material located within a second aperture in the second carrier connected to the second connector material in the at least one aperture in the second carrier.

13. An assembly formed by a plurality of carriers for high thermal usage comprising:

a first carrier having an upper surface, having a lower surface, having a cavity therein extending from the upper surface, a first surface located in a portion of the cavity having at least one connection pad thereon, a second surface located in a portion of the cavity, and a third surface located within a portion of the cavity, a first frusto-conical surface on a portion of the upper surface thereof, a second frusto-conical surface on a portion of the lower surface thereof, a lip on a portion of a lower surface thereof, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower-surface, and at least one circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface, to the at least one connection pad on the lower surface, and to the at least one connection pad on the first surface located in the cavity;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier on a portion of the third surface of the cavity;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

14. The assembly of claim 13, further comprising:

a substrate including a first surface, a second surface, and at least one circuit on the first surface thereof, and at least one second connector connected to the at least one connection pad on the second surface of the first carrier and the at least one circuit on the first surface of the substrate.

15. The assembly of claim 13, wherein the first carrier includes at least one fin on a portion thereof.

16. The assembly of claim 13, further comprising:

a second carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one circuit located in a portion of the cavity connected to one of the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one circuit located in a portion of the cavity of the second carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the second carrier.

17. The assembly of claim 16, further comprising:

a third carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one circuit located in a portion of the cavity connected to one of the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the third carrier;

a first connector between the at least one circuit located in a portion of the cavity of the third carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier, second carrier, and third carrier.

18. The assembly of claim 17, further comprising:

a fourth carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one circuit located in a portion of the cavity connected to one of the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the fourth carrier;

a first connector between the at least one circuit located in a portion of the cavity of the fourth carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the fourth carrier.