Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer

• US 7,829,998 B2
• Filed: 09/25/2007
• Issued: 11/09/2010
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Chua, Linda Pei Ee, Do, Byung Tai, Kuan, Heap Hoe
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US11/861,244
• Publication Number:
  US 20080272464A1
• Time in Patent Office: 1,141 Days
• Field of Search: None
• US Class Current: 257/698
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.

Claims

1. A semiconductor wafer, comprising:

a plurality of semiconductor die each with a plurality of contact pads disposed on a first surface of the semiconductor;

a trench formed between the semiconductor die;

an organic material deposited in the trench;

a plurality of conductive vias formed through the organic material, wherein a width of the conductive vias is less than a width of the organic material in the trench;

a plurality of conductive traces formed over the first surface electrically connecting a first portion of the conductive vias to the contact pads, wherein a second portion of the conductive vias is electrically isolated from the conductive traces;

a plurality of redistribution layer (RDL) nodes formed over a second surface of the semiconductor die opposite the first surface, the RDL nodes extending across the second surface of the semiconductor die to route electrical signals to areas on the second surface including a central region of the semiconductor die for vertical electrical interconnect, wherein a first portion of the RDL nodes is electrically connected to the conductive vias and a second portion of the RDL nodes is electrically isolated from the conductive vias; and

a plurality of repassivation layers formed on the second surface of the semiconductor die for electrical isolation between the RDL nodes.

2. The semiconductor wafer of claim 1, wherein a width of the trench is increased by creating additional space between the semiconductor die.

3. The semiconductor wafer of claim 1, wherein the semiconductor wafer is singulated through the conductive vias to separate the semiconductor die.

4. The semiconductor wafer of claim 1, further including a plurality of side-by-side conductive vias formed within the organic material.

5. The semiconductor wafer of claim 4, wherein the semiconductor wafer is singulated between the side-by-side conductive vias to separate the semiconductor die.

6. The semiconductor wafer of claim 1, further including a plurality of stacked semiconductor die electrically connected through the RDL nodes and conductive vias.

7. The semiconductor wafer of claim 1, wherein the repassivation layer includes silicon nitride, silicon dioxide, silicon oxynitride, polyimide, benzocyclobutene, or polybenzoxazoles.

8. A semiconductor wafer, comprising:

a plurality of semiconductor die each with a plurality of contact pads disposed on a first surface of the semiconductor;

an organic material formed around the semiconductor die;

a plurality of conductive vias formed through the organic material;

a plurality of conductive traces formed over the first surface electrically connecting a first portion of the conductive vias to the contact pads, wherein a second portion of the conductive vias is electrically isolated from the conductive traces;

a plurality of redistribution layer (RDL) nodes formed over a second surface of the semiconductor die opposite the first surface, the RDL nodes extending across the second surface of the semiconductor die to route electrical signals to areas on the second surface including a central region of the semiconductor die for vertical electrical interconnect, wherein a first portion of the RDL nodes is electrically connected to the conductive vias and a second portion of the RDL nodes is electrically isolated from the conductive vias; and

a plurality of repassivation layers formed on the second surface of the semiconductor die for electrical isolation between the RDL nodes.

9. The semiconductor wafer of claim 8, wherein the semiconductor wafer is singulated through the conductive vias to separate the semiconductor die.

10. The semiconductor wafer of claim 8, further including a plurality of side-by-side conductive vias formed within the organic material.

11. The semiconductor wafer of claim 10, wherein the semiconductor wafer is singulated between the side-by-side conductive vias to separate the semiconductor die.

12. The semiconductor wafer of claim 8, further including a plurality of stacked semiconductor die electrically connected through the RDL nodes and conductive vias.

13. The semiconductor wafer of claim 8, wherein the repassivation layer includes silicon nitride, silicon dioxide, silicon oxynitride, polyimide, benzocyclobutene, or polybenzoxazoles.

14. A semiconductor wafer, comprising:

a plurality of semiconductor die each with a plurality of contact pads disposed on a first surface of the semiconductor;

an organic material formed around the semiconductor die;

a plurality of conductive vias formed through the organic material;

a plurality of conductive traces formed over the first surface electrically connecting the conductive vias to the contact pads;

a plurality of redistribution layer (RDL) nodes formed over a second surface of the semiconductor die opposite the first surface, the RDL nodes extending across the second surface of the semiconductor die to route electrical signals to areas on the second surface including a central region of the semiconductor die for vertical electrical interconnect, wherein a first portion of the RDL nodes is electrically connected to the conductive vias and a second portion of the RDL nodes is electrically isolated from the conductive vias; and

a plurality of repassivation layers formed on the second surface of the semiconductor die for electrical isolation between the RDL nodes.

15. The semiconductor wafer of claim 14, wherein the semiconductor wafer is singulated through the conductive vias to separate the semiconductor die.

16. The semiconductor wafer of claim 14, further including a plurality of side-by-side conductive vias formed within the organic material.

17. The semiconductor wafer of claim 16, wherein the semiconductor wafer is singulated between the side-by-side conductive vias to separate the semiconductor die.

18. The semiconductor wafer of claim 14, further including a plurality of stacked semiconductor die electrically connected through the RDL nodes and conductive vias.

19. The semiconductor wafer of claim 14, wherein the repassivation layer includes silicon nitride, silicon dioxide, silicon oxynitride, polyimide, benzocyclobutene, or polybenzoxazoles.

20. A semiconductor wafer, comprising:

a plurality of semiconductor die each with a plurality of contact pads disposed on a first surface of the semiconductor;

an organic material formed around the semiconductor die;

a plurality of conductive vias formed through the organic material;

a plurality of conductive traces formed over the first surface electrically connecting the conductive vias to the contact pads;

a plurality of redistribution layer (RDL) nodes formed over a second surface of the semiconductor die opposite the first surface, the RDL nodes extending across the second surface of the semiconductor die to route electrical signals to areas on the second surface of the semiconductor die including a central region of the semiconductor die for vertical electrical interconnect; and

a plurality of repassivation layers formed on the second surface of the semiconductor die for electrical isolation between the RDL nodes.

21. The semiconductor wafer of claim 20, wherein the semiconductor wafer is singulated through the conductive vias to separate the semiconductor die.

22. The semiconductor wafer of claim 20, further including a plurality of side-by-side conductive vias formed within the organic material.

23. The semiconductor wafer of claim 22, wherein the semiconductor wafer is singulated between the side-by-side conductive vias to separate the semiconductor die.

24. The semiconductor wafer of claim 20, further including a plurality of stacked semiconductor die electrically connected through the RDL nodes and conductive vias.

25. The semiconductor wafer of claim 20, wherein the repassivation layer includes silicon nitride, silicon dioxide, silicon oxynitride, polyimide, benzocyclobutene, or polybenzoxazoles.