Low power single-rail-input voltage level shifter

• US 7,830,175 B1
• Filed: 11/12/2008
• Issued: 11/09/2010
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Yang, Ge, Young, Charles Chew-Yuen, Lin, Hwong-Kwo
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): Tran; Thienvu V
• Application Number:
  US12/269,200
• Time in Patent Office: 727 Days
• Field of Search: 326 62- 68, 326 82- 87, 327/333
• US Class Current: 326/68
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.

Claims

1. A voltage level shifter, comprising:

a single-rail input connected to a low-voltage domain; and

a voltage-transition circuit connected to the single-rail input, the voltage-transition circuit being configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of a high-voltage domain;

wherein the voltage-transition circuit includes an input-falling-transition circuit, the input-falling-transition circuit comprising;

a first p-type transistor; and

a first n-type transistor having a drain connected to a drain of the first p-type transistor at an input contact point, the first n-type transistor having a source connected to the single-rail input, the first n-type transistor having a gate connected to a reference voltage, the first p-type transistor having a source connected to a VDDH voltage of the high-voltage domain;

wherein the voltage-transition circuit includes an input-rising-transition circuit, the input-rising-transition circuit comprising;

a second n-type transistor having a gate connected to the single-rail input, the second n-type transistor having a source connected to a ground voltage, the second n-type transistor having a drain connected to an output contact point, the output contact point being connected to a gate of the first p-type transistor of the input-falling-transition circuit;

a second p-type transistor having a drain connected to the output contact point, the second p-type transistor having a gate connected to the input contact point of the input-falling-transition circuit; and

a third p-type transistor connected in series with the second p-type transistor, the third p-type transistor having a drain connected to a source of the second p-type transistor, the third p-type transistor having a source connected to the VDDH voltage of the high-voltage domain, the third p-type transistor having a gate connected to the single-rail input.

2. The voltage level shifter of claim 1, wherein the output contact point is connected to an input of an inverter, and an output of the inverter is an output node.

3. The voltage level shifter of claim 1, wherein the first n-type transistor has a threshold voltage, the reference voltage is defined such that a difference between the reference voltage and a voltage of the single-rail input is at least one of less than the threshold voltage when the voltage of the single-rail input is a VDDL voltage of the low-voltage domain or greater than the threshold voltage when a voltage of the output contact point is the VDDH voltage of the high-voltage domain.

4. The voltage level shifter of claim 1, wherein the second n-type transistor is sized such that a change in a voltage of the single-rail input from a ground voltage to a VDDL voltage of the low-voltage domain triggers a voltage of the output contact point to change from the VDDH voltage of the high-voltage domain to the ground voltage.

5. The voltage level shifter of claim 1, wherein the third p-type transistor is at least partially on when a voltage of the single-rail input is a VDDL voltage of the low-voltage domain.

6. The voltage level shifter of claim 1, wherein the second p-type transistor corresponds to a p-type blocking transistor that prevents a substantially high current path from forming between the VDDH voltage of the high-voltage domain and a ground voltage when the voltage of the single-rail input is a VDDL voltage.