Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same

• US 7,830,698 B2
• Filed: 05/27/2008
• Issued: 11/09/2010
• Est. Priority Date: 04/11/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Ping, Er-Xuan, Kumar, Tanmay, Chen, Xiying, Xu, Huiwen, Nguyen, Dat, Samachisa, George, Yen, Bing K.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/153,872
• Publication Number:
  US 20090257265A1
• Time in Patent Office: 896 Days
• Field of Search: 365/46, 365/100
• US Class Current: 365/148
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.

Claims

1. A nonvolatile memory cell comprising a steering element located in series with a storage element, wherein the storage element comprises a carbon resistivity switching resistivity switching material and the memory cell comprises a rewritable cell having multiple memory levels, wherein a height of the carbon resistivity switching material in a first direction from a first conductive electrode to a second conductive electrode is greater than a thickness of the resistivity switching material in second direction perpendicular to the first direction.

2. The cell of claim 1, wherein the steering element comprises a diode or a transistor and the carbon resistivity switching material comprises at least one of carbon nanotube, amorphous carbon, polycrystalline carbon or graphene resistivity switching material.

3. The cell of claim 2, wherein the steering element comprises a p-i-n polysilicon diode and the carbon resistivity switching material comprises polycrystalline carbon.

4. The cell of claim 1, wherein the resistivity switching material comprises a thin film disposed at least partially on a sidewall of an insulating feature such that a thickness of at least a portion of the thin film is oriented in a perpendicular direction to a current flow direction between the first and the second conductive electrodes.

5. The cell of claim 4, wherein the thin film is formed on the sidewall of the insulating feature by a sidewall spacer etch such that the thin film does not contact a storage element of an adjacent cell.

6. The cell of claim 1, wherein the cell comprises more than two memory levels and is suitable for at least ten programming cycles.

7. A method of programming a nonvolatile memory cell comprising a steering element located in series with a storage element, wherein the storage element comprises a carbon material, the method comprising placing the cell into at least two different memory levels for at least two programming cycles, wherein the carbon material comprises polycrystalline carbon having a first Raman spectrum peak between 1300 and 1350 cm⁻

1 and a second Raman spectrum peak between 1600 and 1650 cm<sup>−

1</sup>.

8. The method of claim 7, wherein the step of placing the cell into at least two different memory levels comprises:

applying a reset pulse to change a resistivity state of the carbon material from a first state to a second state; and

applying a first set pulse to change a resistivity state of the carbon material from a second state to a third state.

9. The method of claim 8, further comprising:

applying a second set pulse to change a resistivity state of the carbon material from the third state to a fourth state; and

applying a third set pulse to change a resistivity state of the carbon material from the fourth state to the first state.

10. The method of claim 9, further comprising performing a second programming cycle comprising:

applying the reset pulse to change a resistivity state of the carbon material from the first state to the second state;

applying the first set pulse to change a resistivity state of the carbon material from the second state to the third state;

applying the second set pulse to change a resistivity state of the carbon material from the third state to the fourth state; and

applying the third set pulse to change a resistivity state of the carbon material from the fourth state to the first state.

11. The method of claim 10, further comprising performing at least fifty programming cycles.

12. The method of claim 9, wherein:

the reset pulse and the first, second and third set pulses comprise forward bias pulses; and

the reset pulse has a larger amplitude than the first, second and third set pulses.

13. The method of claim 7, wherein the memory cell comprises a portion of a monolithic three dimensional array of nonvolatile memory cells.

14. The method of claim 7, wherein the steering element comprises a diode or a transistor.

15. The method of claim 7, wherein the steering element comprises a p-i-n polysilicon diode.

16. The method of claim 7, further comprising testing the cell in nitrogen ambient at a temperature of about 200°

C.

17. A method of programming a nonvolatile memory cell comprising a diode steering element located in series with a carbon material storage element, comprising:

performing a first programming cycle comprising;

applying a reset pulse to change a resistivity state of the carbon material from a first state to a second state; and

applying a first set pulse to change a resistivity state of the carbon material from a second state to a third state;

applying a second set pulse to change a resistivity state of the carbon material from the third state to a fourth state; and

applying a third set pulse to change a resistivity state of the carbon material from the fourth state to the first state; and

performing a second programming cycle comprising;

applying the reset pulse to change a resistivity state of the carbon material from the first state to the second state;

applying the first set pulse to change a resistivity state of the carbon material from the second state to the third state;

applying the second set pulse to change a resistivity state of the carbon material from the third state to the fourth state; and

applying the third set pulse to change a resistivity state of the carbon material from the fourth state to the first state.

18. The method of claim 17, wherein the carbon material comprises polycrystalline carbon having a first Raman spectrum peak between 1300 and 1350 cm⁻

1 and a second Raman spectrum peak between 1600 and 1650 cm<sup>−

1</sup>.

19. The method of claim 17, further comprising performing at least fifty programming cycles.

20. A method of programming a nonvolatile memory cell comprising a steering element located in series with a storage element, wherein the storage element comprises a carbon material, the method comprising placing the cell into at least two different memory levels for at least two programming cycles;

wherein the step of placing the cell into at least two different memory levels during a first programming cycle comprises;

applying a reset pulse to change a resistivity state of the carbon material from a first state to a second state;

applying a first set pulse to change a resistivity state of the carbon material from a second state to a third state;

applying a second set pulse to change a resistivity state of the carbon material from the third state to a fourth state; and

applying a third set pulse to change a resistivity state of the carbon material from the fourth state to the first state; and

further comprising performing a second programming cycle comprising;

applying the reset pulse to change a resistivity state of the carbon material from the first state to the second state;

applying the first set pulse to change a resistivity state of the carbon material from the second state to the third state;

applying the second set pulse to change a resistivity state of the carbon material from the third state to the fourth state; and

applying the third set pulse to change a resistivity state of the carbon material from the fourth state to the first state;

wherein;

the reset pulse and the first, second and third set pulses comprise forward bias pulses; and

the reset pulse has a larger amplitude than the first, second and third set pulses.

21. The method of claim 20, further comprising performing at least fifty programming cycles.

22. The method of claim 20, wherein the memory cell comprises a portion of a monolithic three dimensional array of nonvolatile memory cells.

23. The method of claim 20, wherein the steering element comprises a diode or a transistor and the carbon material comprises at least one of carbon nanotube, amorphous carbon, polycrystalline carbon or graphene resistivity switching material.

24. The method of claim 20, wherein the carbon material comprises polycrystalline carbon having a first Raman spectrum peak between 1300 and 1350 cm⁻

1 and a second Raman spectrum peak between 1600 and 1650 cm<sup>−

1</sup>, and wherein the steering element comprises a p-i-n polysilicon diode.

25. A method of programming a nonvolatile memory cell comprising a steering element located in series with a storage element, wherein the storage element comprises a carbon material, the method comprising placing the cell into at least two different memory levels for at least two programming cycles and further comprising testing the cell in nitrogen ambient at a temperature of about 200°

C.