Variable time division multiplex transmission system

• US 7,830,906 B2
• Filed: 09/19/2007
• Issued: 11/09/2010
• Est. Priority Date: 12/28/2001
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kondoh, Hitoshi, Satoh, Masahito, Nakao, Shigetoshi
• Primary Examiner(s): Ahmed; Salman
• Application Number:
  US11/858,052
• Publication Number:
  US 20080069151A1
• Time in Patent Office: 1,147 Days
• Field of Search: 370/410, 370/468, 370/352, 370/423, 709/228, 710/9, 710/10, 710/4, 710/107, 710/110, 713/500
• US Class Current: 370/423
• CPC Class Codes: G06F 13/372 using a time-dependent priority, e.g. individually loaded time counters or time slot
• CPC Class Codes: H04J 3/1682 Allocation of channels according to the instantaneous demands of the users, e.g. concentrated multiplexers, statistical multiplexers
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5675 Timeslot assignment, e.g. TDMA
• CPC Class Codes: H04L 47/10 Flow control; Congestion control

Abstract

A time division multiplex transmission system transmits information on multiple channels by using a transmission path with variable time division multiplexing. The variable time division multiplex transmission system of this invention is equipped with multiple channel devices 30 and a single transmission path 5 connected to these multiple channel devices. The multiple channel devices 30 transmit or receive data over the transmission path. Additionally, the system is equipped with a circuit that determines consecutive time slots for using the transmission path, and each of the channel devices transmits or receives data using consecutive time slots. Data can be transmitted in two or more different transmission bands, and the different transmission bands are realized by making the number of time slots used for a communication frame different.

Claims

1. A system comprising:

a master device having a clock terminal, a frame terminal, a data-in terminal, and a data-out terminal, wherein a frame synchronous signal is received through the frame terminal, and wherein master device supplies a device identifier setting command through its data-out terminal in synchronization with a frame synchronous signal; and

a plurality of slave devices that are coupled to one another in a cascading sequence through daisy-chain input and output terminals within each of the slave devices, wherein each slave device includes;

a clock input terminal coupled to the clock signal of the master device;

a frame terminal coupled to the frame signal terminal of the master device;

a data-in terminal coupled to the data-out terminal of the master device;

a data-out terminal coupled to the data-in terminal of the master device;

a device ID assignment circuit coupled to each of its daisy-chain input and output terminals, wherein the device ID assignment circuit includes;

a sequence initiation control circuit that outputs a sequence signal that indicates a device identifier decision sequence in response to the device identifier setting command and the frame synchronous signal;

a counter that counts the clock signal in response to the sequence signal;

a token generation circuit that generates a device identifier setting token for a subsequent slave device in the sequence in response to the clock signal and one of a predetermined logic signal from the master device and the device identifier setting token from a previous slave device; and

a time slot allocation circuit coupled to each of its daisy-chain input and output terminals.

2. The system of claim 1, wherein the sequence initiation control circuit further comprises:

a D flip-flop having an input terminal coupled to the data-in terminal of its slave device and a clock terminal; and

an inverter that is coupled between the frame terminal of its slave device and the clock terminal of the D flip-flop.

3. The system of claim 1, wherein the token generation circuit flirt her comprises:

a token differentiation circuit that is coupled to the daisy-chain input terminal of its slave device;

a header differentiation circuit that is coupled to the data-in terminal of its slave device and the daisy-chain input terminal of its slave device;

a header token production circuit that is coupled to the header differentiation circuit, the sequence initiation control circuit, the clock terminal of its slave device, and the token differentiation circuit; and

a downstream token production circuit that is coupled to the clock terminal of its slave device, the sequence initiation control circuit, and the token differentiation circuit.

4. The system of claim 3, wherein the token differentiation circuit further comprises a multiplexer having:

a first input terminal coupled to the daisy-chain input terminal of its slave device;

a second input terminal coupled to the header token production circuit; and

a selection terminal coupled to the header differentiation circuit.

5. The system of claim 3, wherein the header differentiation circuit further comprises:

an AND gate that is coupled to the data-in terminal of its slave device and a clock terminal and the daisy-chain input terminal of its slave device; and

a D flip-flop having an input terminal coupled to the AND gate, a clock terminal coupled to the sequence initiation control circuit, and an output terminal coupled to the header token production circuit and the token differentiation circuit.

6. The system of claim 3, wherein the header token production circuit further comprises:

a first D flip-flop having a clock terminal coupled to the clock terminal of its slave device, an input terminal coupled to the header differentiation circuit, and an output terminal;

a second D flip-flop having an input coupled to the output of the first D flip-flop, an clock input coupled to the clock terminal of its slave device, and an output terminal;

an inverter coupled to the output of the second D flip-flop; and

an AND gate coupled to the inverter, the clock terminal of its slave device, and the token differentiation circuit.

7. A system comprising:

a master device having a clock terminal, a frame terminal, a data-in terminal, and a data-out terminal; and

a plurality of slave devices that are coupled to one another in a cascading sequence through daisy-chain input and output terminals within each of the slave devices, wherein each slave device includes;

a clock input terminal coupled to the clock signal of the master device;

a frame terminal coupled to the frame signal terminal of the master device;

a data-in terminal coupled to the data-out terminal of the master device;

a data-out terminal coupled to the data-in terminal of the master device;

a device ID assignment circuit coupled to each of its daisy-chain input and output terminals; and

a time slot allocation circuit coupled to each of its daisy-chain input and output terminals, wherein the time slot allocation circuit includes;

a time slot position designation circuit coupled to the clock terminal of its slave device and the frame terminal of its slave device;

a source token circuit coupled to the clock terminal of its slave device, the daisy-chain input terminal of its slave device, and the frame terminal of its slave device;

a token production circuit coupled to the time slot position designation circuit, the source token circuit, and the daisy-chain output terminal of its slave device;

a time slot differentiation circuit coupled to the token production circuit; and

memory coupled to the time slot differentiation circuit, the data-in terminal of its slave device, and the clock terminal of its slave device.

8. The system of claim 7, wherein the time slot position designation circuit further comprises:

a bit counter coupled to the clock terminal of its slave device and the frame terminal of its slave device; and

an AND gate coupled to the bit counter.

9. The system of claim 7, wherein the source token circuit further comprises:

a header token production circuit the clock terminal of its slave device and the frame terminal of its slave device; and

a multiplexer coupled to the header token production circuit and the daisy-chain input terminal of its slave device.

10. The system of claim 7, wherein the token production circuit further comprises a plurality of token propagation circuits coupled in series with one another.

11. The system of claim 10, wherein the time slot differentiation circuit further comprises a plurality of AND gates, wherein each AND gate is coupled to at least one of the token propagation circuits and the time slot position designation circuit.