Detection of timing errors in programmable logic devices

• US 7,831,856 B1
• Filed: 04/03/2008
• Issued: 11/09/2010
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Sun, Shangzhi, He, Jianshe, Liu, Liren
• Primary Examiner(s): Maskulinski; Michael C
• Application Number:
  US12/061,885
• Time in Patent Office: 950 Days
• Field of Search: 714/700, 714/731, 714/744, 714/2
• US Class Current: 714/2
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

In one example, a method of detecting timing errors in a configuration of a programmable logic device (PLD) includes performing a timing analysis on the PLD configuration. The PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block. The method includes calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer. The first delay and the second delay are provided by the timing analysis. The method includes determining whether the PLD configuration satisfies the time constraint based on the slack value.

Claims

1. A computer-implemented method of detecting timing errors in a configuration of a programmable logic device (PLD), the method comprising:

performing a timing analysis on the PLD configuration, wherein the PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block, wherein the first and second clock signals originate from a reference clock signal;

calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer, wherein the first delay and the second delay are measured relative to the reference clock signal and are provided by the timing analysis; and

determining whether the PLD configuration satisfies the time constraint based on the slack value.

2. The method of claim 1, further comprising selectively incrementing or decrementing the slack value by a period of one of the clock signals until the slack value is within a predetermined range prior to the determining.

3. The method of claim 1, wherein the time constraint is a setup time constraint, wherein the slack value is a setup time slack value.

4. The method of claim 1, wherein the time constraint is a hold time constraint, wherein the slack value is a hold time slack value.

5. The method of claim 1, wherein a frequency of the first clock signal is approximately twice a frequency of the second clock signal.

6. The method of claim 1, wherein a frequency of the second clock signal is approximately twice a frequency of the first clock signal.

7. The method of claim 1, wherein the time constraint is a setup time constraint, wherein the slack value is a setup time slack value, the method further comprising:

calculating a hold time slack value associated with the data transfer using the first delay, the second delay, and a hold time constraint associated with the data transfer; and

determining whether the PLD configuration satisfies the hold time constraint based on the hold time slack value.

8. The method of claim 1, wherein the PLD is configured to perform the data transfer on rising and falling edges of the first clock signal.

9. A computer readable medium on which is stored a computer program for performing the method of claim 1.

10. A system comprising:

one or more processors; and

one or more memories adapted to store a plurality of computer readable instructions which when executed by the one or more processors are adapted to cause the system to perform a method of detecting timing errors in a configuration of a programmable logic device (PLD), the method comprising;

performing a timing analysis on the PLD configuration, wherein the PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block,

calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer, wherein the first delay and the second delay are provided by the timing analysis, and

determining whether the PLD configuration satisfies the time constraint based on the slack value,

wherein a frequency of one of the first and second clock signals is approximately twice the frequency of the other of the first and second clock signals.

11. The system of claim 10, wherein the method further comprises selectively incrementing or decrementing the slack value by a period of one of the clock signals until the slack value is within a predetermined range prior to the determining.

12. The system of claim 10, wherein the time constraint is a setup time constraint, wherein the slack value is a setup time slack value.

13. The system of claim 10, wherein the time constraint is a hold time constraint, wherein the slack value is a hold time slack value.

14. The system of claim 10, wherein the first and second clock signals originate from a reference clock signal, wherein the first and second delays are measured relative to the reference clock signal.

15. The system of claim 10, wherein the time constraint is a setup time constraint, wherein the slack value is a setup time slack value, wherein the method further comprises:

calculating a hold time slack value associated with the data transfer using the first delay, the second delay, and a hold time constraint associated with the data transfer; and

determining whether the PLD configuration satisfies the hold time constraint based on the hold time slack value.

16. The system of claim 10, wherein the PLD is configured to perform the data transfer on rising and falling edges of the first clock signal.

17. A computer-implemented method of detecting timing errors in a configuration of a programmable logic device (PLD), the method comprising:

performing a timing analysis on the PLD configuration, wherein the PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block;

calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer, are provided by the timing analysis; and

determining whether the PLD configuration satisfies the time constraint based on the slack value,

wherein a frequency of one of the first and second clock signals is approximately twice the frequency of the other of the first and second clock signals.

18. A computer readable medium on which is stored a computer program for performing the method of claim 17.