Semiconductor device

• US 7,832,647 B2
• Filed: 06/22/2007
• Issued: 11/16/2010
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami, Kurokawa, Yoshiyuki, Ikeda, Takayuki
• Primary Examiner(s): Lee; Seung H
• Application Number:
  US11/812,990
• Publication Number:
  US 20080011861A1
• Time in Patent Office: 1,243 Days
• Field of Search: 235/492
• US Class Current: 235/492
• CPC Class Codes: G06F 1/189 Power distribution
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card

Abstract

A semiconductor device such as an RFID, which can easily generate a given stable potential, is provided. Circuits included in a semiconductor device are categorized depending on whether a given stable power source potential is necessary. A power source potential generated from a wireless signal received by an antenna with the use of the antenna and a rectifier circuit is supplied to a circuit which needs a given stable power source potential through a regulator. On the other hand, a power source potential generated by the rectifier circuit is supplied to a circuit other than the circuit which needs the arbitrary power source potential. Thus, a semiconductor device including a regulator circuit easily designed with a smaller layout can be provided, and the semiconductor device can easily generate a given stable power source potential.

Claims

1. A semiconductor device comprising:

an antenna;

a rectifier circuit;

a regulator circuit;

a first circuit including a clock generating circuit; and

a second circuit including a demodulation circuit and a modulation circuit,

wherein a signal which is received by the antenna is supplied to the rectifier circuit,

wherein a first power source potential outputted from the rectifier circuit is supplied to the regulator circuit and the second circuit, and

wherein a second power source potential outputted from the regulator circuit is supplied to the first circuit.

2. The semiconductor device according to claim 1, wherein the first circuit and the second circuit are connected through a level shifter circuit.

3. A semiconductor device comprising:

an antenna;

a rectifier circuit;

a first regulator circuit;

a second regulator circuit;

a first circuit including a clock generating circuit; and

a second circuit including a demodulation circuit and a modulation circuit,

wherein a signal which is received by the antenna is supplied to the rectifier circuit,

wherein a first power source potential outputted from the rectifier circuit is supplied to the first regulator circuit and the second regulator circuit,

wherein a second power source potential outputted from the first regulator circuit is supplied to the first circuit, and

wherein a third power source potential outputted from the second regulator circuit is supplied to the second circuit.

4. The semiconductor device according to claim 3, wherein the first circuit and the second circuit are connected through a level shifter circuit.

5. A semiconductor device comprising:

an antenna;

a rectifier circuit;

a regulator circuit;

a voltage limiter circuit;

a first circuit including a clock generating circuit; and

a second circuit including a demodulation circuit and a modulation circuit,

wherein a signal which is received by the antenna is supplied to the rectifier circuit,

wherein a first power source potential outputted from the rectifier circuit is supplied to the regulator circuit and the voltage limiter circuit,

wherein a second power source potential outputted from the regulator circuit is supplied to the first circuit, and

wherein a third power source potential outputted from the voltage limiter circuit is supplied to the second circuit.

6. The semiconductor device according to claim 5, wherein the first circuit and the second circuit are connected through a level shifter circuit.