Thin film transistor array panel and method of manufacturing the same
First Claim
1. A method of manufacturing a TFT array panel comprising:
- forming a plurality of thin film transistors each having a gate electrode, a source electrode, and a drain electrode;
forming an insulating layer on the thin film transistors;
forming a first conductive layer electrically connected to the drain electrodes on the insulating layer;
forming a second conductive layer on the first conductive layer;
forming a photoresist layer including first portions and second portions thinner than the first portions;
selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and
selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.
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Abstract
The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.
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Citations
19 Claims
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1. A method of manufacturing a TFT array panel comprising:
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forming a plurality of thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of manufacturing a TFT array panel comprising:
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forming a gate line; forming a semiconductor, a data line and a drain electrode on the gate line; forming a passivation layer and an organic insulating layer on the data line and the drain electrode; sequentially depositing an amorphous ITO layer and a first conductive layer on the organic insulating layer; forming a photoresist layer including first portions and second portions thinner than the first portions on the first conductive layer; selectively etching the first conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the amorphous ITO layer with a second etchant by using the photoresist layer and the first conductive layer as etch blockers; etching the photoresist layer to remove the second portions and to expose the first conductive layer; and selectively etching the exposed portions of the first conductive layer with the first etchant by using the first portions of the photoresist layer as an etch blocker. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification