Method of manufacturing a closed cell trench MOSFET

• US 7,833,863 B1
• Filed: 04/22/2008
• Issued: 11/16/2010
• Est. Priority Date: 12/02/2003
• Status: Expired due to Fees

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva N, Xu, Robert
• Primary Examiner(s): Fulk; Steven J
• Application Number:
  US12/107,738
• Time in Patent Office: 938 Days
• Field of Search: 438/270, 257/331, 257/E21.429
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.

Claims

1. A method of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

depositing a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity;

etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches;

forming a dielectric proximate said plurality of trenches;

doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches with said first type of impurity;

doping said first semiconductor layer proximate the bottoms of said second set of said plurality of trenches with a second type of impurity;

depositing a second semiconductor layer in said plurality of trenches;

doping a first portion of said first semiconductor layer with said second type of impurity, wherein the first portion of said first semiconductor layer extends below said plurality of trenches; and

doping a second portion of said first semiconductor layer proximate said dielectric with said first type of impurity.

2. The method according to claim 1, wherein said depositing said first semiconductor layer comprises epitaxial depositing silicon lightly doped with phosphorous.

3. The method according to claim 1, wherein:

said doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches comprises implanting said first type of impurity at a first angle such that said first type of impurity is implanted in said first set of said plurality of trenches and not in said second set of said plurality of trenches; and

said doping said second semiconductor layer proximate the bottoms of said second set of said plurality of trenches comprises implanting said second type of impurity at a second angle such that said second type of impurity is implanted in said second set of said plurality of trenches and not in said first set of said plurality of trenches.

4. The method according to claim 1, wherein:

said doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches comprises implanting phosphorous; and

said doping said first semiconductor layer proximate the bottoms of said second set of said plurality of trenches comprises implanting boron.

5. The method according to claim 4, wherein said doping said first portion of said first semiconductor layer with said second type of impurity comprises implanting boron to form a body region.

6. The method according to claim 5, wherein said doping a second portion of said first semiconductor layer proximate said dielectric with said first type of impurity comprises implanting phosphorous to form a source region.

7. The method according to claim 1, wherein said forming a dielectric proximate said plurality of trenches comprises oxidizing said first semiconductor layer proximate said plurality of trenches.

8. The method according to claim 1, wherein said depositing said second semiconductor layer in said plurality of trenches comprises chemical vapor depositing polysilicon heavily doped with phosphorous.

9. A method of fabricating a closed cell trench metal-oxide semiconductor field effect transistor (TMOSFEET) comprising:

depositing a first portion of a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity;

doping said first portion of said first semiconductor layer, wherein a plurality of buried doped regions are formed in said first portion of said first semiconductor layer;

depositing a second portion of said first semiconductor layer upon said first portion of said first semiconductor layer;

etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and said plurality of buried doped regions are aligned proximate the bottom of said first set of said plurality of trenches, and wherein a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches;

doping said first semiconductor layer aligned proximate the bottoms of said second set of said plurality of trenches with an impurity type opposite said plurality of buried doped regions;

forming a dielectric proximate said plurality of trenches;

depositing a second semiconductor layer in said plurality of trenches;

doping a body region of said first semiconductor layer between said plurality of trenches with a second type of impurity; and

doping a source region of said first semiconductor layer between said plurality of trenches and said first region of said first semiconductor layer.

10. The method according to claim 9, wherein said depositing said first semiconductor layer comprises epitaxial depositing a semiconductor material lightly doped with said first type of impurity.

11. The method according to claim 10, wherein said doping said body region of said first semiconductor layer comprises implanting said second type of impurity.

12. The method according to claim 11, wherein said doping said source region of said first semiconductor layer comprises implanting said first type of impurity.

13. The method according to claim 12, wherein said substrate is doped with said first type of impurity.

14. The method according to claim 13, wherein:

said plurality of buried doped regions are doped with said first type of impurity; and

said first semiconductor layer proximate the bottoms of said second set of said plurality of trenches are doped with said second type of impurity.

15. The method according to claim 14, wherein said doping said second semiconductor layer proximate the bottoms of said second set of said plurality of trenches comprises implanting said second type of impurity at a second angle such that said second type of impurity is implanted in said second set of said plurality of trenches and not in said first set of said plurality of trenches.

16. The method according to claim 15, wherein said etching said plurality of trenches is performed until the bottoms of said plurality of trenches extend to said plurality of buried doped regions.