Methods for fabricating semiconductor components and packaged semiconductor components

• US 7,833,881 B2
• Filed: 03/02/2007
• Issued: 11/16/2010
• Est. Priority Date: 03/02/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M.
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): LAURENZI, MARK A
• Application Number:
  US11/681,648
• Publication Number:
  US 20080213976A1
• Time in Patent Office: 1,355 Days
• Field of Search: 257/781, 257/200, 438/106, 438/124, 438/114, 438/460
• US Class Current: 438/460
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05618 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys

Abstract

Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall.

Claims

1. A method of manufacturing semiconductor components, comprising:

forming a plurality of first trenches in lanes between dies on a first side of a semiconductor wafer;

filling at least a portion of the first trenches with a protective material;

forming a plurality of second trenches on a second side of the wafer before cutting through the wafer, wherein the first trenches are at least generally aligned with the second trenches along the lanes;

filling at least a portion of the second trenches with the protective material before cutting through the wafer; and

cutting through the wafer along the lanes after forming the plurality of second trenches and after filling at least a portion of the second trenches.

2. The method of claim 1 wherein:

forming the first trenches comprises cutting the first trenches to a first intermediate depth in the wafer; and

forming the second trenches comprises cutting the second trenches to a second intermediate depth in the wafer, and wherein the sum of the first and second intermediate depths is less than a thickness of the wafer between the first and second sides.

3. The method of claim 1 wherein:

forming the first trenches comprises cutting the first trenches to a first intermediate depth in the wafer; and

forming the second trenches comprises cutting the second trenches to a second intermediate depth in the wafer, and wherein a portion of the semiconductor wafer is between the first trenches and the second trenches.

4. The method of claim 1 wherein:

forming the first trenches comprises cutting the first trenches into the first side;

filling at least a portion of the first trenches with the protective material comprises depositing a polymeric material onto the first side of the wafer;

the method further comprises thinning the wafer before forming the second trenches, wherein the thinning process forms the second side;

forming the second trenches comprises cutting the second trenches into the second side after thinning the wafer; and

filling at least a portion of the second trenches with the protective material comprises depositing a polymeric material onto the second side of the wafer.

5. The method of claim 4 wherein the wafer is initially approximately 700-1000 microns thick, and wherein the thinning procedure reduces a thickness between the first and second sides to approximately 300-500 microns.

6. The method of claim 4 wherein depositing the polymeric material onto the first side comprises molding the polymeric material over the first side and into the first trenches before thinning the wafer, and wherein depositing the polymeric material onto the second side comprises molding the polymeric material over the second side and into the second trenches.

7. The method of claim 1 wherein cutting the wafer along the lanes forms a sidewall around each die between the first and second sides, and wherein the sidewall includes a first portion defined at least in part by the protective material in the first trenches, a second portion defined at least in part by the protective material in the second trenches, and a medial portion between the first and second portions defined at least in part by the semiconductor wafer.

8. The method of claim 1 wherein:

filling at least a portion of the first trenches with the protective material comprises molding a polymeric material over the first side and into the first trenches;

filling at least a portion of the second trenches with the protective material comprises molding a polymeric layer over the second side and into the second trenches; and

cutting the wafer along the lanes separates the dies into individual semiconductor components that have a first exterior cover with a first extension extending toward the second side, a second exterior cover with a second extension extending toward the first side, and a sidewall around each die between the first and second sides, wherein the sidewall includes an exterior portion of the first extension, an exterior portion of the second extension, and an exposed portion of the semiconductor wafer between the first and second extensions.

9. The method of claim 8 wherein the first exterior cover has a front side portion over the first side and the first extension projects from the front side portion, the second exterior cover has a backside portion over the second side and the second extension projects from the backside portion, and the front side portion, the first extension, the backside portion, and the second extension have at least approximately the same thickness.

20. The method of claim 1 wherein filling a portion of the first trenches comprises filling a portion of the first trenches with a first protective material, and wherein filling a portion of the second trenches comprises filling a portion of the second trenches with a second protective material, the first protective material being different than the second protective material.

21. The method of claim 20 wherein the first and second protective materials have a similar coefficient of thermal expansion.

22. The method of claim 20 wherein at least one of the first and second protective materials contains a filler configured to alter at least one of the coefficient of thermal expansion or the viscosity of the protective material.

10. A method for manufacturing semiconductor components, comprising:

depositing a first protective material on a first side of a semiconductor wafer having a plurality of dies, wherein the first protective material flows into first trenches in lanes between the dies on the first side of the wafer;

depositing a second protective material on a second side of the wafer before separating the wafer along the lanes, the second protective material being different than the first material, wherein the second protective material flows into second trenches in the second side of the wafer that are aligned with the first trenches in the lanes; and

separating the wafer along the lanes after depositing a second protective material on the second side of the wafer.

11. The method of claim 10, further comprising cutting the first trenches into the first side of the wafer before depositing the protective material on the first side of the wafer.

12. The method of claim 10, further comprising:

thinning the wafer to form the second side before depositing the protective material on the second side; and

cutting trenches in the second side after thinning and before depositing the protective material onto the second side of the wafer.

13. The method of claim 10 wherein thinning the wafer comprises grinding the wafer to a thickness of approximately 300-500 microns.

14. The method of claim 10 wherein separating the wafer along the lanes comprises cutting the wafer through the first and second trenches.

15. The method of claim 14 wherein cutting the wafer forms packaged semiconductor components having a first exterior cover with a front side portion over the first side and a first extension projecting from the front side portion, a second exterior cover with a backside portion over the second side and a second extension projecting from the backside portion, and wherein the front side portion, the first extension, the backside portion, and the second extension have at least approximately the same thickness.

23. The method of claim 10 wherein the first and second protective material have a similar coefficient of thermal expansion.

24. The method of claim 10 wherein at least one of the first and second protective material contains a filler that is configured to alter at least one of the coefficient of thermal expansion or the viscosity of the protective material.

16. A method of manufacturing semiconductor components, comprising:

mounting conductive balls to die contacts connected to integrated circuits of dies on a semiconductor wafer, wherein the die contacts are at a first side of the wafer;

cutting first trenches into the first side of the wafer along lanes adjacent to the dies, wherein the first trenches have a first depth into the wafer;

molding a polymeric material onto the first side and into the first trenches;

thinning the wafer to a second side opposite the first side;

cutting second trenches into the second side of the wafer after the thinning procedure, wherein the second trenches are aligned with the first trenches along the lanes, and wherein the second trenches have a second depth into the wafer, such that the second trenches do not extend into the first trenches;

molding the polymeric material onto the second side and into the second trenches; and

cutting the wafer along the lanes and through the polymeric material in the second trenches, wherein cutting the wafer forms individual components that have a first exterior cover at the first side with a first extension extending toward the second side, a second exterior cover at the second side with a second extension extending toward the first side, and a sidewall between the first and second sides, wherein the sidewall includes an exterior portion of the first extension, an exterior portion of the second extension, and an exposed portion of the semiconductor wafer between the first and second extensions.

17. The method of claim 16 wherein thinning the wafer comprises grinding the backside of the wafer until the wafer has a thickness not less than 300 microns.

18. The method of claim 16 wherein cutting the wafer along the lanes comprises centering a kerf of the cut in the first and second trenches.

19. The method of claim 16 wherein the first and second exterior covers have at least approximately equal thicknesses.