Method of forming a field effect transistor

• US 7,833,892 B2
• Filed: 02/09/2007
• Issued: 11/16/2010
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US11/704,488
• Publication Number:
  US 20070141821A1
• Time in Patent Office: 1,376 Days
• Field of Search: 438/595, 438/596, 438/682, 438/581, 438/592, 438/655, 438/583, 438/585, 438/184, 438/303, 438/308, 438/630, 438/649, 438/651
• US Class Current: 438/595
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Claims

1. A method of forming a field effect transistor, comprising:

forming a gate electrode of a field effect transistor over a silicon-comprising substrate, the gate electrode comprising a sidewall;

forming a first electrically insulative anisotropically etched sidewall spacer over the sidewall of the gate electrode;

forming a second anisotropically etched sidewall spacer over and in direct physical contact with the first sidewall spacer, the second anisotropically etched sidewall spacer being distinct from the first sidewall spacer and the second anisotropically etched sidewall spacer comprising a combination of an electrically conductive material, an electrically insulative material, and a semiconductive material;

depositing metal over the first and second sidewall spacers and over silicon of a source/drain region of the transistor proximate the second sidewall spacer; and

annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide on the source/drain region which is spaced from the first sidewall spacer.

2. A method of forming a field effect transistor, comprising:

forming a gate electrode of a field effect transistor over a silicon-comprising substrate, the gate electrode comprising a sidewall;

forming a first electrically insulative anisotropically etched sidewall spacer over the sidewall of the gate electrode;

forming a second anisotropically etched sidewall spacer over and in direct physical contact with the first sidewall spacer, the second anisotropically etched sidewall spacer being distinct from the first sidewall spacer and the second anisotropically etched sidewall spacer comprising a combination of an electrically conductive material, an electrically insulative material, and a semiconductive material;

depositing metal over the first and second sidewall spacers and over silicon of a source/drain region of the transistor proximate the second sidewall spacer;

annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide on the source/drain region which is spaced from the first sidewall spacer; and

removing the second sidewall spacer from the substrate after the annealing.

3. A method of forming a field effect transistor, comprising:

forming a gate electrode of a field effect transistor over a silicon-comprising substrate, the gate electrode comprising a first sidewall and a second sidewall on opposite sides of the gate electrode;

forming a first electrically insulative anisotropically etched sidewall spacer over each of the first and second sidewalls of the gate electrode;

depositing masking material over the gate electrode and over the first electrically insulative anisotropically etched sidewall spacer received over each of the first and second sidewalls of the gate electrode;

etching the masking material to expose silicon on one of the opposite sides of the gate electrode and not on the other of the opposite sides of the gate electrode, the etching forming a second anisotropically etched sidewall spacer over and distinct from the first sidewall spacer on the one of the opposite sides and not on the other of the opposite sides;

depositing metal over the first and second sidewall spacers and over silicon of a source/drain region of the transistor proximate the second sidewall spacer; and

annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide on the source/drain region which is spaced from the first sidewall spacer.

4. The method of claim 3 wherein the masking material is electrically insulative.

5. The method of claim 3 wherein the masking material comprises amorphous carbon.

6. The method of claim 3 wherein the masking material comprises transparent carbon.

7. The method of claim 3 wherein the masking material is electrically conductive.

8. The method of claim 7 wherein the masking material comprises a metal nitride.

9. The method of claim 8 wherein the masking material comprises tungsten nitride.

10. The method of claim 8 wherein the masking material comprises titanium nitride.

11. The method of claim 3 wherein the masking material is semiconductive.

12. The method of claim 3 wherein the depositing of the masking material through said etching of the masking material to expose silicon occurs without any photolithographic patterning anywhere on the substrate.

13. The method of claim 3 wherein the etching of the masking material is selective relative to the first and second sidewall spacers.